lib/Target/X86/X86TargetMachine.cpp

   1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the X86 specific subclass of TargetMachine.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86TargetMachine.h"
  15 #include "X86.h"
  16 #include "llvm/PassManager.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/FormattedStream.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 using namespace llvm;
  24
  25 extern "C" void LLVMInitializeX86Target() {
  26   // Register the target.
  27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
  28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
  29 }
  30
  31
  32 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
  33                                          StringRef CPU, StringRef FS,
  34                                          Reloc::Model RM, CodeModel::Model CM)
  35   : X86TargetMachine(T, TT, CPU, FS, RM, CM, false),
  36     DataLayout(getSubtargetImpl()->isTargetDarwin() ?
  37                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
  38                "n8:16:32-S128" :
  39                (getSubtargetImpl()->isTargetCygMing() ||
  40                 getSubtargetImpl()->isTargetWindows()) ?
  41                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
  42                "n8:16:32-S32" :
  43                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
  44                "n8:16:32-S128"),
  45     InstrInfo(*this),
  46     TSInfo(*this),
  47     TLInfo(*this),
  48     JITInfo(*this) {
  49 }
  50
  51
  52 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
  53                                          StringRef CPU, StringRef FS,
  54                                          Reloc::Model RM, CodeModel::Model CM)
  55   : X86TargetMachine(T, TT, CPU, FS, RM, CM, true),
  56     DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
  57                "n8:16:32:64-S128"),
  58     InstrInfo(*this),
  59     TSInfo(*this),
  60     TLInfo(*this),
  61     JITInfo(*this) {
  62 }
  63
  64 /// X86TargetMachine ctor - Create an X86 target.
  65 ///
  66 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
  67                                    StringRef CPU, StringRef FS,
  68                                    Reloc::Model RM, CodeModel::Model CM,
  69                                    bool is64Bit)
  70   : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
  71     Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
  72     FrameLowering(*this, Subtarget),
  73     ELFWriterInfo(is64Bit, true) {
  74   // Determine the PICStyle based on the target selected.
  75   if (getRelocationModel() == Reloc::Static) {
  76     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
  77     Subtarget.setPICStyle(PICStyles::None);
  78   } else if (Subtarget.is64Bit()) {
  79     // PIC in 64 bit mode is always rip-rel.
  80     Subtarget.setPICStyle(PICStyles::RIPRel);
  81   } else if (Subtarget.isTargetCygMing()) {
  82     Subtarget.setPICStyle(PICStyles::None);
  83   } else if (Subtarget.isTargetDarwin()) {
  84     if (getRelocationModel() == Reloc::PIC_)
  85       Subtarget.setPICStyle(PICStyles::StubPIC);
  86     else {
  87       assert(getRelocationModel() == Reloc::DynamicNoPIC);
  88       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
  89     }
  90   } else if (Subtarget.isTargetELF()) {
  91     Subtarget.setPICStyle(PICStyles::GOT);
  92   }
  93
  94   // default to hard float ABI
  95   if (FloatABIType == FloatABI::Default)
  96     FloatABIType = FloatABI::Hard;
  97 }
  98
  99 //===----------------------------------------------------------------------===//
 100 // Command line options for x86
 101 //===----------------------------------------------------------------------===//
 102 static cl::opt<bool>
 103 UseVZeroUpper("x86-use-vzeroupper",
 104   cl::desc("Minimize AVX to SSE transition penalty"),
 105   cl::init(false));
 106
 107 //===----------------------------------------------------------------------===//
 108 // Pass Pipeline Configuration
 109 //===----------------------------------------------------------------------===//
 110
 111 bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
 112                                        CodeGenOpt::Level OptLevel) {
 113   // Install an instruction selector.
 114   PM.add(createX86ISelDag(*this, OptLevel));
 115
 116   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
 117   if (!Subtarget.is64Bit())
 118     PM.add(createGlobalBaseRegPass());
 119
 120   return false;
 121 }
 122
 123 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
 124                                       CodeGenOpt::Level OptLevel) {
 125   PM.add(createX86MaxStackAlignmentHeuristicPass());
 126   return false;  // -print-machineinstr shouldn't print after this.
 127 }
 128
 129 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
 130                                        CodeGenOpt::Level OptLevel) {
 131   PM.add(createX86FloatingPointStackifierPass());
 132   return true;  // -print-machineinstr should print after this.
 133 }
 134
 135 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
 136                                       CodeGenOpt::Level OptLevel) {
 137   bool ShouldPrint = false;
 138   if (OptLevel != CodeGenOpt::None &&
 139       (Subtarget.hasSSE2() || Subtarget.hasAVX())) {
 140     PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
 141     ShouldPrint = true;
 142   }
 143
 144   if (Subtarget.hasAVX() && UseVZeroUpper) {
 145     PM.add(createX86IssueVZeroUpperPass());
 146     ShouldPrint = true;
 147   }
 148
 149   return ShouldPrint;
 150 }
 151
 152 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
 153                                       CodeGenOpt::Level OptLevel,
 154                                       JITCodeEmitter &JCE) {
 155   PM.add(createX86JITCodeEmitterPass(*this, JCE));
 156
 157   return false;
 158 }