1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
27 extern "C" void LLVMInitializeX86Target() {
28 // Register the target.
29 RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
30 RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
33 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
34 if (TT.isOSBinFormatMachO()) {
35 if (TT.getArch() == Triple::x86_64)
36 return make_unique<X86_64MachoTargetObjectFile>();
37 return make_unique<TargetLoweringObjectFileMachO>();
40 if (TT.isOSLinux() || TT.isOSNaCl())
41 return make_unique<X86LinuxNaClTargetObjectFile>();
42 if (TT.isOSBinFormatELF())
43 return make_unique<X86ELFTargetObjectFile>();
44 if (TT.isKnownWindowsMSVCEnvironment())
45 return make_unique<X86WindowsTargetObjectFile>();
46 if (TT.isOSBinFormatCOFF())
47 return make_unique<TargetLoweringObjectFileCOFF>();
48 llvm_unreachable("unknown subtarget type");
51 static std::string computeDataLayout(const Triple &TT) {
52 // X86 is little endian
53 std::string Ret = "e";
55 Ret += DataLayout::getManglingComponent(TT);
56 // X86 and x32 have 32 bit pointers.
57 if ((TT.isArch64Bit() &&
58 (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
62 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
63 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
68 // Some ABIs align long double to 128 bits, others to 32.
71 else if (TT.isArch64Bit() || TT.isOSDarwin())
76 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
78 Ret += "-n8:16:32:64";
82 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
83 if (!TT.isArch64Bit() && TT.isOSWindows())
91 /// X86TargetMachine ctor - Create an X86 target.
93 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
94 StringRef FS, const TargetOptions &Options,
95 Reloc::Model RM, CodeModel::Model CM,
97 : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options,
99 TLOF(createTLOF(Triple(getTargetTriple()))),
100 Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
101 // Windows stack unwinder gets confused when execution flow "falls through"
102 // after a call to 'noreturn' function.
103 // To prevent that, we emit a trap for 'unreachable' IR instructions.
104 // (which on X86, happens to be the 'ud2' instruction)
105 if (Subtarget.isTargetWin64())
106 this->Options.TrapUnreachable = true;
108 // TODO: By default, all reciprocal estimate operations are off because
109 // that matches the behavior before TargetRecip was added (except for btver2
110 // which used subtarget features to enable this type of codegen).
111 // We should change this to match GCC behavior where everything but
112 // scalar division estimates are turned on by default with -ffast-math.
113 this->Options.Reciprocals.setDefaults("all", false, 1);
118 X86TargetMachine::~X86TargetMachine() {}
121 X86TargetMachine::getSubtargetImpl(const Function &F) const {
122 Attribute CPUAttr = F.getFnAttribute("target-cpu");
123 Attribute FSAttr = F.getFnAttribute("target-features");
125 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
126 ? CPUAttr.getValueAsString().str()
128 std::string FS = !FSAttr.hasAttribute(Attribute::None)
129 ? FSAttr.getValueAsString().str()
132 // FIXME: This is related to the code below to reset the target options,
133 // we need to know whether or not the soft float flag is set on the
134 // function before we can generate a subtarget. We also need to use
135 // it as a key for the subtarget since that can be the only difference
136 // between two functions.
138 F.hasFnAttribute("use-soft-float") &&
139 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
140 // If the soft float attribute is set on the function turn on the soft float
141 // subtarget feature.
143 FS += FS.empty() ? "+soft-float" : ",+soft-float";
145 auto &I = SubtargetMap[CPU + FS];
147 // This needs to be done before we create a new subtarget since any
148 // creation will depend on the TM and the code generation flags on the
149 // function that reside in TargetOptions.
150 resetTargetOptions(F);
151 I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
152 Options.StackAlignmentOverride);
157 //===----------------------------------------------------------------------===//
158 // Command line options for x86
159 //===----------------------------------------------------------------------===//
161 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
162 cl::desc("Minimize AVX to SSE transition penalty"),
165 //===----------------------------------------------------------------------===//
167 //===----------------------------------------------------------------------===//
169 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
170 return TargetIRAnalysis(
171 [this](Function &F) { return TargetTransformInfo(X86TTIImpl(this, F)); });
175 //===----------------------------------------------------------------------===//
176 // Pass Pipeline Configuration
177 //===----------------------------------------------------------------------===//
180 /// X86 Code Generator Pass Configuration Options.
181 class X86PassConfig : public TargetPassConfig {
183 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
184 : TargetPassConfig(TM, PM) {}
186 X86TargetMachine &getX86TargetMachine() const {
187 return getTM<X86TargetMachine>();
190 void addIRPasses() override;
191 bool addInstSelector() override;
192 bool addILPOpts() override;
193 bool addPreISel() override;
194 void addPreRegAlloc() override;
195 void addPostRegAlloc() override;
196 void addPreEmitPass() override;
197 void addPreSched2() override;
201 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
202 return new X86PassConfig(this, PM);
205 void X86PassConfig::addIRPasses() {
206 addPass(createAtomicExpandPass(&getX86TargetMachine()));
208 TargetPassConfig::addIRPasses();
211 bool X86PassConfig::addInstSelector() {
212 // Install an instruction selector.
213 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
215 // For ELF, cleanup any local-dynamic TLS accesses.
216 if (Triple(TM->getTargetTriple()).isOSBinFormatELF() &&
217 getOptLevel() != CodeGenOpt::None)
218 addPass(createCleanupLocalDynamicTLSPass());
220 addPass(createX86GlobalBaseRegPass());
225 bool X86PassConfig::addILPOpts() {
226 addPass(&EarlyIfConverterID);
230 bool X86PassConfig::addPreISel() {
231 // Only add this pass for 32-bit x86 Windows.
232 Triple TT(TM->getTargetTriple());
233 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
234 addPass(createX86WinEHStatePass());
238 void X86PassConfig::addPreRegAlloc() {
239 addPass(createX86CallFrameOptimization());
242 void X86PassConfig::addPostRegAlloc() {
243 addPass(createX86FloatingPointStackifierPass());
246 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
248 void X86PassConfig::addPreEmitPass() {
249 if (getOptLevel() != CodeGenOpt::None)
250 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
253 addPass(createX86IssueVZeroUpperPass());
255 if (getOptLevel() != CodeGenOpt::None) {
256 addPass(createX86PadShortFunctions());
257 addPass(createX86FixupLEAs());