1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/ADT/Statistic.h"
28 X86VectorEnum llvm::X86Vector = NoSSE;
31 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
32 cl::desc("Disable the ssa-based peephole optimizer "
33 "(defaults to disabled)"));
34 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
35 cl::desc("Disable the X86 asm printer, for use "
36 "when profiling the code generator."));
39 // FIXME: This should eventually be handled with target triples and
41 cl::opt<X86VectorEnum, true>
43 cl::desc("Enable SSE support in the X86 target:"),
45 clEnumValN(SSE, "sse", " Enable SSE support"),
46 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
47 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
49 cl::location(X86Vector), cl::init(NoSSE));
52 // Register the target.
53 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
56 unsigned X86TargetMachine::getJITMatchQuality() {
57 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
64 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
65 if (M.getEndianness() == Module::LittleEndian &&
66 M.getPointerSize() == Module::Pointer32)
67 return 10; // Direct match
68 else if (M.getEndianness() != Module::AnyEndianness ||
69 M.getPointerSize() != Module::AnyPointerSize)
70 return 0; // Match for some other target
72 return getJITMatchQuality()/2;
75 /// X86TargetMachine ctor - Create an ILP32 architecture model
77 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
78 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
79 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, -4),
84 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
85 // does to emit statically compiled machine code.
86 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
88 // FIXME: Implement efficient support for garbage collection intrinsics.
89 PM.add(createLowerGCPass());
91 // FIXME: Implement the invoke/unwind instructions!
92 PM.add(createLowerInvokePass());
94 // FIXME: Implement the switch instruction in the instruction selector!
95 PM.add(createLowerSwitchPass());
97 // Make sure that no unreachable blocks are instruction selected.
98 PM.add(createUnreachableBlockEliminationPass());
100 PM.add(createX86SimpleInstructionSelector(*this));
102 // Run optional SSA-based machine code optimizations next...
104 PM.add(createX86SSAPeepholeOptimizerPass());
106 // Print the instruction selected machine code...
107 if (PrintMachineCode)
108 PM.add(createMachineFunctionPrinterPass(&std::cerr));
110 // Perform register allocation to convert to a concrete x86 representation
111 PM.add(createRegisterAllocator());
113 if (PrintMachineCode)
114 PM.add(createMachineFunctionPrinterPass(&std::cerr));
116 PM.add(createX86FloatingPointStackifierPass());
118 if (PrintMachineCode)
119 PM.add(createMachineFunctionPrinterPass(&std::cerr));
121 // Insert prolog/epilog code. Eliminate abstract frame index references...
122 PM.add(createPrologEpilogCodeInserter());
124 PM.add(createX86PeepholeOptimizerPass());
126 if (PrintMachineCode) // Print the register-allocated code
127 PM.add(createX86CodePrinterPass(std::cerr, *this));
130 PM.add(createX86CodePrinterPass(Out, *this));
132 // Delete machine code for this function
133 PM.add(createMachineCodeDeleter());
135 return false; // success!
138 /// addPassesToJITCompile - Add passes to the specified pass manager to
139 /// implement a fast dynamic compiler for this target. Return true if this is
140 /// not supported for this target.
142 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
143 // FIXME: Implement efficient support for garbage collection intrinsics.
144 PM.add(createLowerGCPass());
146 // FIXME: Implement the invoke/unwind instructions!
147 PM.add(createLowerInvokePass());
149 // FIXME: Implement the switch instruction in the instruction selector!
150 PM.add(createLowerSwitchPass());
152 // Make sure that no unreachable blocks are instruction selected.
153 PM.add(createUnreachableBlockEliminationPass());
155 PM.add(createX86SimpleInstructionSelector(TM));
157 // Run optional SSA-based machine code optimizations next...
159 PM.add(createX86SSAPeepholeOptimizerPass());
161 // FIXME: Add SSA based peephole optimizer here.
163 // Print the instruction selected machine code...
164 if (PrintMachineCode)
165 PM.add(createMachineFunctionPrinterPass(&std::cerr));
167 // Perform register allocation to convert to a concrete x86 representation
168 PM.add(createRegisterAllocator());
170 if (PrintMachineCode)
171 PM.add(createMachineFunctionPrinterPass(&std::cerr));
173 PM.add(createX86FloatingPointStackifierPass());
175 if (PrintMachineCode)
176 PM.add(createMachineFunctionPrinterPass(&std::cerr));
178 // Insert prolog/epilog code. Eliminate abstract frame index references...
179 PM.add(createPrologEpilogCodeInserter());
181 PM.add(createX86PeepholeOptimizerPass());
183 if (PrintMachineCode) // Print the register-allocated code
184 PM.add(createX86CodePrinterPass(std::cerr, TM));