1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include "llvm/Target/TargetOptions.h"
24 extern "C" void LLVMInitializeX86Target() {
25 // Register the target.
26 RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
27 RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
30 void X86TargetMachine::anchor() { }
32 static std::string computeDataLayout(const X86Subtarget &ST) {
33 // X86 is little endian
34 std::string Ret = "e";
36 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
37 // X86 and x32 have 32 bit pointers.
38 if (ST.isTarget64BitILP32() || !ST.is64Bit())
41 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
42 if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC() ||
48 // Some ABIs align long double to 128 bits, others to 32.
49 if (ST.isTargetNaCl())
51 else if (ST.is64Bit() || ST.isTargetDarwin())
56 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
58 Ret += "-n8:16:32:64";
62 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
63 if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC()))
71 /// X86TargetMachine ctor - Create an X86 target.
73 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
74 StringRef CPU, StringRef FS,
75 const TargetOptions &Options,
76 Reloc::Model RM, CodeModel::Model CM,
78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
80 FrameLowering(*this, Subtarget),
81 InstrItins(Subtarget.getInstrItineraryData()),
82 DL(computeDataLayout(*getSubtargetImpl())),
87 // Determine the PICStyle based on the target selected.
88 if (getRelocationModel() == Reloc::Static) {
89 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
90 Subtarget.setPICStyle(PICStyles::None);
91 } else if (Subtarget.is64Bit()) {
92 // PIC in 64 bit mode is always rip-rel.
93 Subtarget.setPICStyle(PICStyles::RIPRel);
94 } else if (Subtarget.isTargetCOFF()) {
95 Subtarget.setPICStyle(PICStyles::None);
96 } else if (Subtarget.isTargetDarwin()) {
97 if (getRelocationModel() == Reloc::PIC_)
98 Subtarget.setPICStyle(PICStyles::StubPIC);
100 assert(getRelocationModel() == Reloc::DynamicNoPIC);
101 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
103 } else if (Subtarget.isTargetELF()) {
104 Subtarget.setPICStyle(PICStyles::GOT);
107 // default to hard float ABI
108 if (Options.FloatABIType == FloatABI::Default)
109 this->Options.FloatABIType = FloatABI::Hard;
114 //===----------------------------------------------------------------------===//
115 // Command line options for x86
116 //===----------------------------------------------------------------------===//
118 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
119 cl::desc("Minimize AVX to SSE transition penalty"),
122 // Temporary option to control early if-conversion for x86 while adding machine
125 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
126 cl::desc("Enable early if-conversion on X86"));
128 //===----------------------------------------------------------------------===//
129 // X86 Analysis Pass Setup
130 //===----------------------------------------------------------------------===//
132 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
133 // Add first the target-independent BasicTTI pass, then our X86 pass. This
134 // allows the X86 pass to delegate to the target independent layer when
136 PM.add(createBasicTargetTransformInfoPass(this));
137 PM.add(createX86TargetTransformInfoPass(this));
141 //===----------------------------------------------------------------------===//
142 // Pass Pipeline Configuration
143 //===----------------------------------------------------------------------===//
146 /// X86 Code Generator Pass Configuration Options.
147 class X86PassConfig : public TargetPassConfig {
149 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
150 : TargetPassConfig(TM, PM) {}
152 X86TargetMachine &getX86TargetMachine() const {
153 return getTM<X86TargetMachine>();
156 const X86Subtarget &getX86Subtarget() const {
157 return *getX86TargetMachine().getSubtargetImpl();
160 bool addInstSelector() override;
161 bool addILPOpts() override;
162 bool addPreRegAlloc() override;
163 bool addPostRegAlloc() override;
164 bool addPreEmitPass() override;
168 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
169 return new X86PassConfig(this, PM);
172 bool X86PassConfig::addInstSelector() {
173 // Install an instruction selector.
174 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
176 // For ELF, cleanup any local-dynamic TLS accesses.
177 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
178 addPass(createCleanupLocalDynamicTLSPass());
180 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
181 if (!getX86Subtarget().is64Bit())
182 addPass(createGlobalBaseRegPass());
187 bool X86PassConfig::addILPOpts() {
188 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
189 addPass(&EarlyIfConverterID);
195 bool X86PassConfig::addPreRegAlloc() {
196 return false; // -print-machineinstr shouldn't print after this.
199 bool X86PassConfig::addPostRegAlloc() {
200 addPass(createX86FloatingPointStackifierPass());
201 return true; // -print-machineinstr should print after this.
204 bool X86PassConfig::addPreEmitPass() {
205 bool ShouldPrint = false;
206 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
207 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
211 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
212 addPass(createX86IssueVZeroUpperPass());
216 if (getOptLevel() != CodeGenOpt::None &&
217 getX86Subtarget().padShortFunctions()) {
218 addPass(createX86PadShortFunctions());
221 if (getOptLevel() != CodeGenOpt::None &&
222 getX86Subtarget().LEAusesAG()){
223 addPass(createX86FixupLEAs());
230 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
231 JITCodeEmitter &JCE) {
232 PM.add(createX86JITCodeEmitterPass(*this, JCE));