1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Target/TargetMachineImpls.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Transforms/Scalar.h"
22 #include "Support/CommandLine.h"
23 #include "Support/Statistic.h"
27 cl::opt<bool> PrintCode("print-machineinstrs",
28 cl::desc("Print generated machine code"));
29 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
30 cl::desc("Use the 'simple' X86 instruction selector"));
31 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
32 cl::desc("Disable the ssa-based peephole optimizer (defaults to disabled)"));
35 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
36 // that implements the X86 backend.
38 TargetMachine *llvm::allocateX86TargetMachine(const Module &M) {
39 return new X86TargetMachine(M);
43 /// X86TargetMachine ctor - Create an ILP32 architecture model
45 X86TargetMachine::X86TargetMachine(const Module &M)
46 : TargetMachine("X86", true, 4, 4, 4, 4, 4),
47 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4),
52 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
53 // does to emit statically compiled machine code.
54 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
56 // FIXME: Implement the switch instruction in the instruction selector!
57 PM.add(createLowerSwitchPass());
59 // FIXME: Implement the invoke/unwind instructions!
60 PM.add(createLowerInvokePass());
62 // FIXME: The code generator does not properly handle functions with
63 // unreachable basic blocks.
64 PM.add(createCFGSimplificationPass());
67 PM.add(createX86SimpleInstructionSelector(*this));
69 PM.add(createX86PatternInstructionSelector(*this));
71 // Run optional SSA-based machine code optimizations next...
73 PM.add(createX86SSAPeepholeOptimizerPass());
75 // Print the instruction selected machine code...
77 PM.add(createMachineFunctionPrinterPass());
79 // Perform register allocation to convert to a concrete x86 representation
80 PM.add(createRegisterAllocator());
83 PM.add(createMachineFunctionPrinterPass());
85 PM.add(createX86FloatingPointStackifierPass());
88 PM.add(createMachineFunctionPrinterPass());
90 // Insert prolog/epilog code. Eliminate abstract frame index references...
91 PM.add(createPrologEpilogCodeInserter());
93 PM.add(createX86PeepholeOptimizerPass());
95 if (PrintCode) // Print the register-allocated code
96 PM.add(createX86CodePrinterPass(std::cerr, *this));
98 PM.add(createX86CodePrinterPass(Out, *this));
100 // Delete machine code for this function
101 PM.add(createMachineCodeDeleter());
103 return false; // success!
106 /// addPassesToJITCompile - Add passes to the specified pass manager to
107 /// implement a fast dynamic compiler for this target. Return true if this is
108 /// not supported for this target.
110 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
111 // FIXME: Implement the switch instruction in the instruction selector!
112 PM.add(createLowerSwitchPass());
114 // FIXME: Implement the invoke/unwind instructions!
115 PM.add(createLowerInvokePass());
117 // FIXME: The code generator does not properly handle functions with
118 // unreachable basic blocks.
119 PM.add(createCFGSimplificationPass());
122 PM.add(createX86SimpleInstructionSelector(TM));
124 PM.add(createX86PatternInstructionSelector(TM));
126 // Run optional SSA-based machine code optimizations next...
128 PM.add(createX86SSAPeepholeOptimizerPass());
130 // FIXME: Add SSA based peephole optimizer here.
132 // Print the instruction selected machine code...
134 PM.add(createMachineFunctionPrinterPass());
136 // Perform register allocation to convert to a concrete x86 representation
137 PM.add(createRegisterAllocator());
140 PM.add(createMachineFunctionPrinterPass());
142 PM.add(createX86FloatingPointStackifierPass());
145 PM.add(createMachineFunctionPrinterPass());
147 // Insert prolog/epilog code. Eliminate abstract frame index references...
148 PM.add(createPrologEpilogCodeInserter());
150 PM.add(createX86PeepholeOptimizerPass());
152 if (PrintCode) // Print the register-allocated code
153 PM.add(createX86CodePrinterPass(std::cerr, TM));