1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
25 extern "C" void LLVMInitializeX86Target() {
26 // Register the target.
27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 void X86_32TargetMachine::anchor() { }
33 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
34 StringRef CPU, StringRef FS,
35 const TargetOptions &Options,
36 Reloc::Model RM, CodeModel::Model CM,
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
39 DL(getSubtargetImpl()->isTargetDarwin() ?
40 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
42 (getSubtargetImpl()->isTargetCygMing() ||
43 getSubtargetImpl()->isTargetWindows()) ?
44 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
46 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
54 void X86_64TargetMachine::anchor() { }
56 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
57 StringRef CPU, StringRef FS,
58 const TargetOptions &Options,
59 Reloc::Model RM, CodeModel::Model CM,
61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
62 // The x32 ABI dictates the ILP32 programming model for x64.
63 DL(getSubtargetImpl()->isTarget64BitILP32() ?
64 "e-p:32:32-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
66 "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
74 /// X86TargetMachine ctor - Create an X86 target.
76 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
77 StringRef CPU, StringRef FS,
78 const TargetOptions &Options,
79 Reloc::Model RM, CodeModel::Model CM,
82 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
83 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
84 FrameLowering(*this, Subtarget),
85 InstrItins(Subtarget.getInstrItineraryData()){
86 // Determine the PICStyle based on the target selected.
87 if (getRelocationModel() == Reloc::Static) {
88 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
89 Subtarget.setPICStyle(PICStyles::None);
90 } else if (Subtarget.is64Bit()) {
91 // PIC in 64 bit mode is always rip-rel.
92 Subtarget.setPICStyle(PICStyles::RIPRel);
93 } else if (Subtarget.isTargetCygMing()) {
94 Subtarget.setPICStyle(PICStyles::None);
95 } else if (Subtarget.isTargetDarwin()) {
96 if (getRelocationModel() == Reloc::PIC_)
97 Subtarget.setPICStyle(PICStyles::StubPIC);
99 assert(getRelocationModel() == Reloc::DynamicNoPIC);
100 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
102 } else if (Subtarget.isTargetELF()) {
103 Subtarget.setPICStyle(PICStyles::GOT);
106 // default to hard float ABI
107 if (Options.FloatABIType == FloatABI::Default)
108 this->Options.FloatABIType = FloatABI::Hard;
111 //===----------------------------------------------------------------------===//
112 // Command line options for x86
113 //===----------------------------------------------------------------------===//
115 UseVZeroUpper("x86-use-vzeroupper",
116 cl::desc("Minimize AVX to SSE transition penalty"),
119 // Temporary option to control early if-conversion for x86 while adding machine
122 X86EarlyIfConv("x86-early-ifcvt",
123 cl::desc("Enable early if-conversion on X86"));
125 //===----------------------------------------------------------------------===//
126 // X86 Analysis Pass Setup
127 //===----------------------------------------------------------------------===//
129 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
130 // Add first the target-independent BasicTTI pass, then our X86 pass. This
131 // allows the X86 pass to delegate to the target independent layer when
133 PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
134 PM.add(createX86TargetTransformInfoPass(this));
138 //===----------------------------------------------------------------------===//
139 // Pass Pipeline Configuration
140 //===----------------------------------------------------------------------===//
143 /// X86 Code Generator Pass Configuration Options.
144 class X86PassConfig : public TargetPassConfig {
146 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
147 : TargetPassConfig(TM, PM) {}
149 X86TargetMachine &getX86TargetMachine() const {
150 return getTM<X86TargetMachine>();
153 const X86Subtarget &getX86Subtarget() const {
154 return *getX86TargetMachine().getSubtargetImpl();
157 virtual bool addInstSelector();
158 virtual bool addILPOpts();
159 virtual bool addPreRegAlloc();
160 virtual bool addPostRegAlloc();
161 virtual bool addPreEmitPass();
165 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
166 return new X86PassConfig(this, PM);
169 bool X86PassConfig::addInstSelector() {
170 // Install an instruction selector.
171 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
173 // For ELF, cleanup any local-dynamic TLS accesses.
174 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
175 addPass(createCleanupLocalDynamicTLSPass());
177 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
178 if (!getX86Subtarget().is64Bit())
179 addPass(createGlobalBaseRegPass());
184 bool X86PassConfig::addILPOpts() {
185 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
186 addPass(&EarlyIfConverterID);
192 bool X86PassConfig::addPreRegAlloc() {
193 return false; // -print-machineinstr shouldn't print after this.
196 bool X86PassConfig::addPostRegAlloc() {
197 addPass(createX86FloatingPointStackifierPass());
198 return true; // -print-machineinstr should print after this.
201 bool X86PassConfig::addPreEmitPass() {
202 bool ShouldPrint = false;
203 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
204 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
208 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
209 addPass(createX86IssueVZeroUpperPass());
213 if (getOptLevel() != CodeGenOpt::None &&
214 getX86Subtarget().padShortFunctions()) {
215 addPass(createX86PadShortFunctions());
222 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
223 JITCodeEmitter &JCE) {
224 PM.add(createX86JITCodeEmitterPass(*this, JCE));