1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Support/TargetRegistry.h"
25 extern "C" void LLVMInitializeX86Target() {
26 // Register the target.
27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 void X86_32TargetMachine::anchor() { }
33 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
34 StringRef CPU, StringRef FS,
35 const TargetOptions &Options,
36 Reloc::Model RM, CodeModel::Model CM,
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
39 DataLayout(getSubtargetImpl()->isTargetDarwin() ?
40 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
42 (getSubtargetImpl()->isTargetCygMing() ||
43 getSubtargetImpl()->isTargetWindows()) ?
44 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
46 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
54 void X86_64TargetMachine::anchor() { }
56 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
57 StringRef CPU, StringRef FS,
58 const TargetOptions &Options,
59 Reloc::Model RM, CodeModel::Model CM,
61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
62 DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
70 /// X86TargetMachine ctor - Create an X86 target.
72 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
80 FrameLowering(*this, Subtarget),
81 ELFWriterInfo(is64Bit, true),
82 InstrItins(Subtarget.getInstrItineraryData()){
83 // Determine the PICStyle based on the target selected.
84 if (getRelocationModel() == Reloc::Static) {
85 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
86 Subtarget.setPICStyle(PICStyles::None);
87 } else if (Subtarget.is64Bit()) {
88 // PIC in 64 bit mode is always rip-rel.
89 Subtarget.setPICStyle(PICStyles::RIPRel);
90 } else if (Subtarget.isTargetCygMing()) {
91 Subtarget.setPICStyle(PICStyles::None);
92 } else if (Subtarget.isTargetDarwin()) {
93 if (getRelocationModel() == Reloc::PIC_)
94 Subtarget.setPICStyle(PICStyles::StubPIC);
96 assert(getRelocationModel() == Reloc::DynamicNoPIC);
97 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
99 } else if (Subtarget.isTargetELF()) {
100 Subtarget.setPICStyle(PICStyles::GOT);
103 // default to hard float ABI
104 if (Options.FloatABIType == FloatABI::Default)
105 this->Options.FloatABIType = FloatABI::Hard;
108 //===----------------------------------------------------------------------===//
109 // Command line options for x86
110 //===----------------------------------------------------------------------===//
112 UseVZeroUpper("x86-use-vzeroupper",
113 cl::desc("Minimize AVX to SSE transition penalty"),
116 //===----------------------------------------------------------------------===//
117 // Pass Pipeline Configuration
118 //===----------------------------------------------------------------------===//
121 /// X86 Code Generator Pass Configuration Options.
122 class X86PassConfig : public TargetPassConfig {
124 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
125 : TargetPassConfig(TM, PM) {}
127 X86TargetMachine &getX86TargetMachine() const {
128 return getTM<X86TargetMachine>();
131 const X86Subtarget &getX86Subtarget() const {
132 return *getX86TargetMachine().getSubtargetImpl();
135 virtual bool addInstSelector();
136 virtual bool addPreRegAlloc();
137 virtual bool addPostRegAlloc();
138 virtual bool addPreEmitPass();
142 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
143 X86PassConfig *PC = new X86PassConfig(this, PM);
145 if (Subtarget.hasCMov())
146 PC->enablePass(&EarlyIfConverterID);
151 bool X86PassConfig::addInstSelector() {
152 // Install an instruction selector.
153 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
155 // For ELF, cleanup any local-dynamic TLS accesses.
156 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
157 addPass(createCleanupLocalDynamicTLSPass());
159 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
160 if (!getX86Subtarget().is64Bit())
161 addPass(createGlobalBaseRegPass());
166 bool X86PassConfig::addPreRegAlloc() {
167 addPass(createX86MaxStackAlignmentHeuristicPass());
168 return false; // -print-machineinstr shouldn't print after this.
171 bool X86PassConfig::addPostRegAlloc() {
172 addPass(createX86FloatingPointStackifierPass());
173 return true; // -print-machineinstr should print after this.
176 bool X86PassConfig::addPreEmitPass() {
177 bool ShouldPrint = false;
178 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
179 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
183 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
184 addPass(createX86IssueVZeroUpperPass());
191 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
192 JITCodeEmitter &JCE) {
193 PM.add(createX86JITCodeEmitterPass(*this, JCE));