1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/ADT/Statistic.h"
28 X86VectorEnum llvm::X86Vector = NoSSE;
30 /// X86TargetMachineModule - Note that this is used on hosts that cannot link
31 /// in a library unless there are references into the library. In particular,
32 /// it seems that it is not possible to get things to work on Win32 without
33 /// this. Though it is unused, do not remove it.
34 extern "C" int X86TargetMachineModule;
35 int X86TargetMachineModule = 0;
38 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
39 cl::desc("Disable the ssa-based peephole optimizer "
40 "(defaults to disabled)"));
41 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
42 cl::desc("Disable the X86 asm printer, for use "
43 "when profiling the code generator."));
44 cl::opt<bool> DisablePatternISel("disable-pattern-isel", cl::Hidden,
45 cl::desc("Disable the pattern isel XXX FIXME"),
49 // FIXME: This should eventually be handled with target triples and
51 cl::opt<X86VectorEnum, true>
53 cl::desc("Enable SSE support in the X86 target:"),
55 clEnumValN(SSE, "sse", " Enable SSE support"),
56 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
57 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
59 cl::location(X86Vector), cl::init(NoSSE));
62 // Register the target.
63 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
66 unsigned X86TargetMachine::getJITMatchQuality() {
67 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
74 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
75 // We strongly match "i[3-9]86-*".
76 std::string TT = M.getTargetTriple();
77 if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
78 TT[4] == '-' && TT[1] - '3' < 6)
81 if (M.getEndianness() == Module::LittleEndian &&
82 M.getPointerSize() == Module::Pointer32)
83 return 10; // Weak match
84 else if (M.getEndianness() != Module::AnyEndianness ||
85 M.getPointerSize() != Module::AnyPointerSize)
86 return 0; // Match for some other target
88 return getJITMatchQuality()/2;
91 /// X86TargetMachine ctor - Create an ILP32 architecture model
93 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
94 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
95 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, -4),
100 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
101 // does to emit statically compiled machine code.
102 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
104 // FIXME: Implement efficient support for garbage collection intrinsics.
105 PM.add(createLowerGCPass());
107 // FIXME: Implement the invoke/unwind instructions!
108 PM.add(createLowerInvokePass());
110 // FIXME: Implement the switch instruction in the instruction selector!
111 PM.add(createLowerSwitchPass());
113 // Make sure that no unreachable blocks are instruction selected.
114 PM.add(createUnreachableBlockEliminationPass());
116 if (DisablePatternISel)
117 PM.add(createX86SimpleInstructionSelector(*this));
119 PM.add(createX86PatternInstructionSelector(*this));
121 // Run optional SSA-based machine code optimizations next...
123 PM.add(createX86SSAPeepholeOptimizerPass());
125 // Print the instruction selected machine code...
126 if (PrintMachineCode)
127 PM.add(createMachineFunctionPrinterPass(&std::cerr));
129 // Perform register allocation to convert to a concrete x86 representation
130 PM.add(createRegisterAllocator());
132 if (PrintMachineCode)
133 PM.add(createMachineFunctionPrinterPass(&std::cerr));
135 PM.add(createX86FloatingPointStackifierPass());
137 if (PrintMachineCode)
138 PM.add(createMachineFunctionPrinterPass(&std::cerr));
140 // Insert prolog/epilog code. Eliminate abstract frame index references...
141 PM.add(createPrologEpilogCodeInserter());
143 PM.add(createX86PeepholeOptimizerPass());
145 if (PrintMachineCode) // Print the register-allocated code
146 PM.add(createX86CodePrinterPass(std::cerr, *this));
149 PM.add(createX86CodePrinterPass(Out, *this));
151 // Delete machine code for this function
152 PM.add(createMachineCodeDeleter());
154 return false; // success!
157 /// addPassesToJITCompile - Add passes to the specified pass manager to
158 /// implement a fast dynamic compiler for this target. Return true if this is
159 /// not supported for this target.
161 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
162 // FIXME: Implement efficient support for garbage collection intrinsics.
163 PM.add(createLowerGCPass());
165 // FIXME: Implement the invoke/unwind instructions!
166 PM.add(createLowerInvokePass());
168 // FIXME: Implement the switch instruction in the instruction selector!
169 PM.add(createLowerSwitchPass());
171 // Make sure that no unreachable blocks are instruction selected.
172 PM.add(createUnreachableBlockEliminationPass());
174 if (DisablePatternISel)
175 PM.add(createX86SimpleInstructionSelector(TM));
177 PM.add(createX86PatternInstructionSelector(TM));
179 // Run optional SSA-based machine code optimizations next...
181 PM.add(createX86SSAPeepholeOptimizerPass());
183 // FIXME: Add SSA based peephole optimizer here.
185 // Print the instruction selected machine code...
186 if (PrintMachineCode)
187 PM.add(createMachineFunctionPrinterPass(&std::cerr));
189 // Perform register allocation to convert to a concrete x86 representation
190 PM.add(createRegisterAllocator());
192 if (PrintMachineCode)
193 PM.add(createMachineFunctionPrinterPass(&std::cerr));
195 PM.add(createX86FloatingPointStackifierPass());
197 if (PrintMachineCode)
198 PM.add(createMachineFunctionPrinterPass(&std::cerr));
200 // Insert prolog/epilog code. Eliminate abstract frame index references...
201 PM.add(createPrologEpilogCodeInserter());
203 PM.add(createX86PeepholeOptimizerPass());
205 if (PrintMachineCode) // Print the register-allocated code
206 PM.add(createX86CodePrinterPass(std::cerr, TM));