1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/ADT/Statistic.h"
28 X86VectorEnum llvm::X86Vector = NoSSE;
29 bool llvm::X86ScalarSSE = false;
31 /// X86TargetMachineModule - Note that this is used on hosts that cannot link
32 /// in a library unless there are references into the library. In particular,
33 /// it seems that it is not possible to get things to work on Win32 without
34 /// this. Though it is unused, do not remove it.
35 extern "C" int X86TargetMachineModule;
36 int X86TargetMachineModule = 0;
39 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
40 cl::desc("Disable the ssa-based peephole optimizer "
41 "(defaults to disabled)"));
42 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
43 cl::desc("Disable the X86 asm printer, for use "
44 "when profiling the code generator."));
45 cl::opt<bool, true> EnableSSEFP("enable-sse-scalar-fp",
46 cl::desc("Perform FP math in SSE regs instead of the FP stack"),
47 cl::location(X86ScalarSSE),
50 // FIXME: This should eventually be handled with target triples and
52 cl::opt<X86VectorEnum, true>
54 cl::desc("Enable SSE support in the X86 target:"),
56 clEnumValN(SSE, "sse", " Enable SSE support"),
57 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
58 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
60 cl::location(X86Vector), cl::init(NoSSE));
62 // Register the target.
63 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
66 unsigned X86TargetMachine::getJITMatchQuality() {
67 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
74 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
75 // We strongly match "i[3-9]86-*".
76 std::string TT = M.getTargetTriple();
77 if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
78 TT[4] == '-' && TT[1] - '3' < 6)
81 if (M.getEndianness() == Module::LittleEndian &&
82 M.getPointerSize() == Module::Pointer32)
83 return 10; // Weak match
84 else if (M.getEndianness() != Module::AnyEndianness ||
85 M.getPointerSize() != Module::AnyPointerSize)
86 return 0; // Match for some other target
88 return getJITMatchQuality()/2;
91 /// X86TargetMachine ctor - Create an ILP32 architecture model
93 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
94 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
96 FrameInfo(TargetFrameInfo::StackGrowsDown,
97 Subtarget.getStackAlignment(), -4),
99 // Scalar SSE FP requires at least SSE2
100 X86ScalarSSE &= X86Vector >= SSE2;
104 // addPassesToEmitFile - We currently use all of the same passes as the JIT
105 // does to emit statically compiled machine code.
106 bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
107 CodeGenFileType FileType) {
108 if (FileType != TargetMachine::AssemblyFile &&
109 FileType != TargetMachine::ObjectFile) return true;
111 // FIXME: Implement efficient support for garbage collection intrinsics.
112 PM.add(createLowerGCPass());
114 // FIXME: Implement the invoke/unwind instructions!
115 PM.add(createLowerInvokePass());
117 // FIXME: Implement the switch instruction in the instruction selector!
118 PM.add(createLowerSwitchPass());
120 // Make sure that no unreachable blocks are instruction selected.
121 PM.add(createUnreachableBlockEliminationPass());
123 // Default to pattern ISel
124 if (PatternISelTriState == 0)
125 PM.add(createX86SimpleInstructionSelector(*this));
127 PM.add(createX86PatternInstructionSelector(*this));
129 // Run optional SSA-based machine code optimizations next...
131 PM.add(createX86SSAPeepholeOptimizerPass());
133 // Print the instruction selected machine code...
134 if (PrintMachineCode)
135 PM.add(createMachineFunctionPrinterPass(&std::cerr));
137 // Perform register allocation to convert to a concrete x86 representation
138 PM.add(createRegisterAllocator());
140 if (PrintMachineCode)
141 PM.add(createMachineFunctionPrinterPass(&std::cerr));
143 PM.add(createX86FloatingPointStackifierPass());
145 if (PrintMachineCode)
146 PM.add(createMachineFunctionPrinterPass(&std::cerr));
148 // Insert prolog/epilog code. Eliminate abstract frame index references...
149 PM.add(createPrologEpilogCodeInserter());
151 PM.add(createX86PeepholeOptimizerPass());
153 if (PrintMachineCode) // Print the register-allocated code
154 PM.add(createX86CodePrinterPass(std::cerr, *this));
159 assert(0 && "Unexpected filetype here!");
160 case TargetMachine::AssemblyFile:
161 PM.add(createX86CodePrinterPass(Out, *this));
163 case TargetMachine::ObjectFile:
164 // FIXME: We only support emission of ELF files for now, this should check
165 // the target triple and decide on the format to write (e.g. COFF on
167 addX86ELFObjectWriterPass(PM, Out, *this);
171 // Delete machine code for this function
172 PM.add(createMachineCodeDeleter());
174 return false; // success!
177 /// addPassesToJITCompile - Add passes to the specified pass manager to
178 /// implement a fast dynamic compiler for this target. Return true if this is
179 /// not supported for this target.
181 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
182 // FIXME: Implement efficient support for garbage collection intrinsics.
183 PM.add(createLowerGCPass());
185 // FIXME: Implement the invoke/unwind instructions!
186 PM.add(createLowerInvokePass());
188 // FIXME: Implement the switch instruction in the instruction selector!
189 PM.add(createLowerSwitchPass());
191 // Make sure that no unreachable blocks are instruction selected.
192 PM.add(createUnreachableBlockEliminationPass());
194 // Default to pattern ISel
195 if (PatternISelTriState == 0)
196 PM.add(createX86SimpleInstructionSelector(TM));
198 PM.add(createX86PatternInstructionSelector(TM));
200 // Run optional SSA-based machine code optimizations next...
202 PM.add(createX86SSAPeepholeOptimizerPass());
204 // FIXME: Add SSA based peephole optimizer here.
206 // Print the instruction selected machine code...
207 if (PrintMachineCode)
208 PM.add(createMachineFunctionPrinterPass(&std::cerr));
210 // Perform register allocation to convert to a concrete x86 representation
211 PM.add(createRegisterAllocator());
213 if (PrintMachineCode)
214 PM.add(createMachineFunctionPrinterPass(&std::cerr));
216 PM.add(createX86FloatingPointStackifierPass());
218 if (PrintMachineCode)
219 PM.add(createMachineFunctionPrinterPass(&std::cerr));
221 // Insert prolog/epilog code. Eliminate abstract frame index references...
222 PM.add(createPrologEpilogCodeInserter());
224 PM.add(createX86PeepholeOptimizerPass());
226 if (PrintMachineCode) // Print the register-allocated code
227 PM.add(createX86CodePrinterPass(std::cerr, TM));
230 bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
231 MachineCodeEmitter &MCE) {
232 PM.add(createX86CodeEmitterPass(MCE));
233 // Delete machine code for this function
234 PM.add(createMachineCodeDeleter());