1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "X86TargetObjectFile.h"
17 #include "X86TargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
27 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
28 cl::desc("Enable the machine combiner pass"),
29 cl::init(true), cl::Hidden);
31 extern "C" void LLVMInitializeX86Target() {
32 // Register the target.
33 RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
34 RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
37 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
38 if (TT.isOSBinFormatMachO()) {
39 if (TT.getArch() == Triple::x86_64)
40 return make_unique<X86_64MachoTargetObjectFile>();
41 return make_unique<TargetLoweringObjectFileMachO>();
44 if (TT.isOSLinux() || TT.isOSNaCl())
45 return make_unique<X86LinuxNaClTargetObjectFile>();
46 if (TT.isOSBinFormatELF())
47 return make_unique<X86ELFTargetObjectFile>();
48 if (TT.isKnownWindowsMSVCEnvironment())
49 return make_unique<X86WindowsTargetObjectFile>();
50 if (TT.isOSBinFormatCOFF())
51 return make_unique<TargetLoweringObjectFileCOFF>();
52 llvm_unreachable("unknown subtarget type");
55 static std::string computeDataLayout(const Triple &TT) {
56 // X86 is little endian
57 std::string Ret = "e";
59 Ret += DataLayout::getManglingComponent(TT);
60 // X86 and x32 have 32 bit pointers.
61 if ((TT.isArch64Bit() &&
62 (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
66 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
67 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
72 // Some ABIs align long double to 128 bits, others to 32.
75 else if (TT.isArch64Bit() || TT.isOSDarwin())
80 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
82 Ret += "-n8:16:32:64";
86 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
87 if (!TT.isArch64Bit() && TT.isOSWindows())
95 /// X86TargetMachine ctor - Create an X86 target.
97 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
98 StringRef CPU, StringRef FS,
99 const TargetOptions &Options,
100 Reloc::Model RM, CodeModel::Model CM,
101 CodeGenOpt::Level OL)
102 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
104 TLOF(createTLOF(getTargetTriple())),
105 Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
106 // Windows stack unwinder gets confused when execution flow "falls through"
107 // after a call to 'noreturn' function.
108 // To prevent that, we emit a trap for 'unreachable' IR instructions.
109 // (which on X86, happens to be the 'ud2' instruction)
110 if (Subtarget.isTargetWin64())
111 this->Options.TrapUnreachable = true;
113 // By default (and when -ffast-math is on), enable estimate codegen for
114 // everything except scalar division. By default, use 1 refinement step for
115 // all operations. Defaults may be overridden by using command-line options.
116 // Scalar division estimates are disabled because they break too much
117 // real-world code. These defaults match GCC behavior.
118 this->Options.Reciprocals.setDefaults("sqrtf", true, 1);
119 this->Options.Reciprocals.setDefaults("divf", false, 1);
120 this->Options.Reciprocals.setDefaults("vec-sqrtf", true, 1);
121 this->Options.Reciprocals.setDefaults("vec-divf", true, 1);
126 X86TargetMachine::~X86TargetMachine() {}
129 X86TargetMachine::getSubtargetImpl(const Function &F) const {
130 Attribute CPUAttr = F.getFnAttribute("target-cpu");
131 Attribute FSAttr = F.getFnAttribute("target-features");
133 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
134 ? CPUAttr.getValueAsString().str()
136 std::string FS = !FSAttr.hasAttribute(Attribute::None)
137 ? FSAttr.getValueAsString().str()
140 // FIXME: This is related to the code below to reset the target options,
141 // we need to know whether or not the soft float flag is set on the
142 // function before we can generate a subtarget. We also need to use
143 // it as a key for the subtarget since that can be the only difference
144 // between two functions.
146 F.hasFnAttribute("use-soft-float") &&
147 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
148 // If the soft float attribute is set on the function turn on the soft float
149 // subtarget feature.
151 FS += FS.empty() ? "+soft-float" : ",+soft-float";
153 auto &I = SubtargetMap[CPU + FS];
155 // This needs to be done before we create a new subtarget since any
156 // creation will depend on the TM and the code generation flags on the
157 // function that reside in TargetOptions.
158 resetTargetOptions(F);
159 I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
160 Options.StackAlignmentOverride);
165 //===----------------------------------------------------------------------===//
166 // Command line options for x86
167 //===----------------------------------------------------------------------===//
169 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
170 cl::desc("Minimize AVX to SSE transition penalty"),
173 //===----------------------------------------------------------------------===//
175 //===----------------------------------------------------------------------===//
177 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
178 return TargetIRAnalysis(
179 [this](Function &F) { return TargetTransformInfo(X86TTIImpl(this, F)); });
183 //===----------------------------------------------------------------------===//
184 // Pass Pipeline Configuration
185 //===----------------------------------------------------------------------===//
188 /// X86 Code Generator Pass Configuration Options.
189 class X86PassConfig : public TargetPassConfig {
191 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
192 : TargetPassConfig(TM, PM) {}
194 X86TargetMachine &getX86TargetMachine() const {
195 return getTM<X86TargetMachine>();
198 void addIRPasses() override;
199 bool addInstSelector() override;
200 bool addILPOpts() override;
201 bool addPreISel() override;
202 void addPreRegAlloc() override;
203 void addPostRegAlloc() override;
204 void addPreEmitPass() override;
205 void addPreSched2() override;
209 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
210 return new X86PassConfig(this, PM);
213 void X86PassConfig::addIRPasses() {
214 addPass(createAtomicExpandPass(&getX86TargetMachine()));
216 TargetPassConfig::addIRPasses();
219 bool X86PassConfig::addInstSelector() {
220 // Install an instruction selector.
221 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
223 // For ELF, cleanup any local-dynamic TLS accesses.
224 if (TM->getTargetTriple().isOSBinFormatELF() &&
225 getOptLevel() != CodeGenOpt::None)
226 addPass(createCleanupLocalDynamicTLSPass());
228 addPass(createX86GlobalBaseRegPass());
233 bool X86PassConfig::addILPOpts() {
234 addPass(&EarlyIfConverterID);
235 if (EnableMachineCombinerPass)
236 addPass(&MachineCombinerID);
240 bool X86PassConfig::addPreISel() {
241 // Only add this pass for 32-bit x86 Windows.
242 const Triple &TT = TM->getTargetTriple();
243 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
244 addPass(createX86WinEHStatePass());
248 void X86PassConfig::addPreRegAlloc() {
249 addPass(createX86CallFrameOptimization());
252 void X86PassConfig::addPostRegAlloc() {
253 addPass(createX86FloatingPointStackifierPass());
256 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
258 void X86PassConfig::addPreEmitPass() {
259 if (getOptLevel() != CodeGenOpt::None)
260 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
263 addPass(createX86IssueVZeroUpperPass());
265 if (getOptLevel() != CodeGenOpt::None) {
266 addPass(createX86PadShortFunctions());
267 addPass(createX86FixupLEAs());