1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/ADT/Statistic.h"
28 X86VectorEnum llvm::X86Vector = NoSSE;
30 /// X86TargetMachineModule - Note that this is used on hosts that cannot link
31 /// in a library unless there are references into the library. In particular,
32 /// it seems that it is not possible to get things to work on Win32 without
33 /// this. Though it is unused, do not remove it.
34 extern "C" int X86TargetMachineModule;
35 int X86TargetMachineModule = 0;
38 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
39 cl::desc("Disable the ssa-based peephole optimizer "
40 "(defaults to disabled)"));
41 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
42 cl::desc("Disable the X86 asm printer, for use "
43 "when profiling the code generator."));
46 // FIXME: This should eventually be handled with target triples and
48 cl::opt<X86VectorEnum, true>
50 cl::desc("Enable SSE support in the X86 target:"),
52 clEnumValN(SSE, "sse", " Enable SSE support"),
53 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
54 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
56 cl::location(X86Vector), cl::init(NoSSE));
59 // Register the target.
60 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
63 unsigned X86TargetMachine::getJITMatchQuality() {
64 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
71 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
72 // We strongly match "i[3-9]86-*".
73 std::string TT = M.getTargetTriple();
74 if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
75 TT[4] == '-' && TT[1] - '3' < 6)
78 if (M.getEndianness() == Module::LittleEndian &&
79 M.getPointerSize() == Module::Pointer32)
80 return 10; // Weak match
81 else if (M.getEndianness() != Module::AnyEndianness ||
82 M.getPointerSize() != Module::AnyPointerSize)
83 return 0; // Match for some other target
85 return getJITMatchQuality()/2;
88 /// X86TargetMachine ctor - Create an ILP32 architecture model
90 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
91 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
92 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, -4),
97 // addPassesToEmitFile - We currently use all of the same passes as the JIT
98 // does to emit statically compiled machine code.
99 bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
100 CodeGenFileType FileType) {
101 if (FileType != TargetMachine::AssemblyFile &&
102 FileType != TargetMachine::ObjectFile) return true;
104 // FIXME: Implement efficient support for garbage collection intrinsics.
105 PM.add(createLowerGCPass());
107 // FIXME: Implement the invoke/unwind instructions!
108 PM.add(createLowerInvokePass());
110 // FIXME: Implement the switch instruction in the instruction selector!
111 PM.add(createLowerSwitchPass());
113 // Make sure that no unreachable blocks are instruction selected.
114 PM.add(createUnreachableBlockEliminationPass());
116 // Default to pattern ISel
117 if (PatternISelTriState == 0)
118 PM.add(createX86SimpleInstructionSelector(*this));
120 PM.add(createX86PatternInstructionSelector(*this));
122 // Run optional SSA-based machine code optimizations next...
124 PM.add(createX86SSAPeepholeOptimizerPass());
126 // Print the instruction selected machine code...
127 if (PrintMachineCode)
128 PM.add(createMachineFunctionPrinterPass(&std::cerr));
130 // Perform register allocation to convert to a concrete x86 representation
131 PM.add(createRegisterAllocator());
133 if (PrintMachineCode)
134 PM.add(createMachineFunctionPrinterPass(&std::cerr));
136 PM.add(createX86FloatingPointStackifierPass());
138 if (PrintMachineCode)
139 PM.add(createMachineFunctionPrinterPass(&std::cerr));
141 // Insert prolog/epilog code. Eliminate abstract frame index references...
142 PM.add(createPrologEpilogCodeInserter());
144 PM.add(createX86PeepholeOptimizerPass());
146 if (PrintMachineCode) // Print the register-allocated code
147 PM.add(createX86CodePrinterPass(std::cerr, *this));
152 assert(0 && "Unexpected filetype here!");
153 case TargetMachine::AssemblyFile:
154 PM.add(createX86CodePrinterPass(Out, *this));
156 case TargetMachine::ObjectFile:
157 // FIXME: We only support emission of ELF files for now, this should check
158 // the target triple and decide on the format to write (e.g. COFF on
160 PM.add(createX86ELFObjectWriterPass(Out, *this));
164 // Delete machine code for this function
165 PM.add(createMachineCodeDeleter());
167 return false; // success!
170 /// addPassesToJITCompile - Add passes to the specified pass manager to
171 /// implement a fast dynamic compiler for this target. Return true if this is
172 /// not supported for this target.
174 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
175 // FIXME: Implement efficient support for garbage collection intrinsics.
176 PM.add(createLowerGCPass());
178 // FIXME: Implement the invoke/unwind instructions!
179 PM.add(createLowerInvokePass());
181 // FIXME: Implement the switch instruction in the instruction selector!
182 PM.add(createLowerSwitchPass());
184 // Make sure that no unreachable blocks are instruction selected.
185 PM.add(createUnreachableBlockEliminationPass());
187 // Default to pattern ISel
188 if (PatternISelTriState == 0)
189 PM.add(createX86SimpleInstructionSelector(TM));
191 PM.add(createX86PatternInstructionSelector(TM));
193 // Run optional SSA-based machine code optimizations next...
195 PM.add(createX86SSAPeepholeOptimizerPass());
197 // FIXME: Add SSA based peephole optimizer here.
199 // Print the instruction selected machine code...
200 if (PrintMachineCode)
201 PM.add(createMachineFunctionPrinterPass(&std::cerr));
203 // Perform register allocation to convert to a concrete x86 representation
204 PM.add(createRegisterAllocator());
206 if (PrintMachineCode)
207 PM.add(createMachineFunctionPrinterPass(&std::cerr));
209 PM.add(createX86FloatingPointStackifierPass());
211 if (PrintMachineCode)
212 PM.add(createMachineFunctionPrinterPass(&std::cerr));
214 // Insert prolog/epilog code. Eliminate abstract frame index references...
215 PM.add(createPrologEpilogCodeInserter());
217 PM.add(createX86PeepholeOptimizerPass());
219 if (PrintMachineCode) // Print the register-allocated code
220 PM.add(createX86CodePrinterPass(std::cerr, TM));