1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/IntrinsicLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineImpls.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "Support/CommandLine.h"
24 #include "Support/Statistic.h"
28 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
29 cl::desc("Use the 'simple' X86 instruction selector"));
30 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
31 cl::desc("Disable the ssa-based peephole optimizer "
32 "(defaults to disabled)"));
33 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
34 cl::desc("Disable the X86 asm printer, for use "
35 "when profiling the code generator."));
38 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
39 // that implements the X86 backend.
41 TargetMachine *llvm::allocateX86TargetMachine(const Module &M,
42 IntrinsicLowering *IL) {
43 return new X86TargetMachine(M, IL);
47 /// X86TargetMachine ctor - Create an ILP32 architecture model
49 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
50 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
51 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4),
56 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
57 // does to emit statically compiled machine code.
58 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
60 // FIXME: Implement the invoke/unwind instructions!
61 PM.add(createLowerInvokePass());
63 // FIXME: The code generator does not properly handle functions with
64 // unreachable basic blocks.
65 PM.add(createCFGSimplificationPass());
67 // FIXME: Implement the switch instruction in the instruction selector!
68 PM.add(createLowerSwitchPass());
70 // FIXME: Add support for the select instruction natively.
71 PM.add(createLowerSelectPass(true));
74 PM.add(createX86SimpleInstructionSelector(*this));
76 PM.add(createX86PatternInstructionSelector(*this));
78 // Run optional SSA-based machine code optimizations next...
80 PM.add(createX86SSAPeepholeOptimizerPass());
82 // Print the instruction selected machine code...
84 PM.add(createMachineFunctionPrinterPass(&std::cerr));
86 // Perform register allocation to convert to a concrete x86 representation
87 PM.add(createRegisterAllocator());
90 PM.add(createMachineFunctionPrinterPass(&std::cerr));
92 PM.add(createX86FloatingPointStackifierPass());
95 PM.add(createMachineFunctionPrinterPass(&std::cerr));
97 // Insert prolog/epilog code. Eliminate abstract frame index references...
98 PM.add(createPrologEpilogCodeInserter());
100 PM.add(createX86PeepholeOptimizerPass());
102 if (PrintMachineCode) // Print the register-allocated code
103 PM.add(createX86CodePrinterPass(std::cerr, *this));
106 PM.add(createX86CodePrinterPass(Out, *this));
108 // Delete machine code for this function
109 PM.add(createMachineCodeDeleter());
111 return false; // success!
114 /// addPassesToJITCompile - Add passes to the specified pass manager to
115 /// implement a fast dynamic compiler for this target. Return true if this is
116 /// not supported for this target.
118 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
120 // FIXME: Implement the invoke/unwind instructions!
121 PM.add(createLowerInvokePass());
123 // FIXME: The code generator does not properly handle functions with
124 // unreachable basic blocks.
125 PM.add(createCFGSimplificationPass());
127 // FIXME: Implement the switch instruction in the instruction selector!
128 PM.add(createLowerSwitchPass());
130 // FIXME: Add support for the select instruction natively.
131 PM.add(createLowerSelectPass(true));
134 PM.add(createX86SimpleInstructionSelector(TM));
136 PM.add(createX86PatternInstructionSelector(TM));
138 // Run optional SSA-based machine code optimizations next...
140 PM.add(createX86SSAPeepholeOptimizerPass());
142 // FIXME: Add SSA based peephole optimizer here.
144 // Print the instruction selected machine code...
145 if (PrintMachineCode)
146 PM.add(createMachineFunctionPrinterPass(&std::cerr));
148 // Perform register allocation to convert to a concrete x86 representation
149 PM.add(createRegisterAllocator());
151 if (PrintMachineCode)
152 PM.add(createMachineFunctionPrinterPass(&std::cerr));
154 PM.add(createX86FloatingPointStackifierPass());
156 if (PrintMachineCode)
157 PM.add(createMachineFunctionPrinterPass(&std::cerr));
159 // Insert prolog/epilog code. Eliminate abstract frame index references...
160 PM.add(createPrologEpilogCodeInserter());
162 PM.add(createX86PeepholeOptimizerPass());
164 if (PrintMachineCode) // Print the register-allocated code
165 PM.add(createX86CodePrinterPass(std::cerr, TM));