1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Target/TargetMachineImpls.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Transforms/Scalar.h"
22 #include "Support/CommandLine.h"
23 #include "Support/Statistic.h"
27 cl::opt<bool> PrintCode("print-machineinstrs",
28 cl::desc("Print generated machine code"));
29 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
30 cl::desc("Use the 'simple' X86 instruction selector"));
31 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
32 cl::desc("Disable the ssa-based peephole optimizer (defaults to disabled)"));
35 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
36 // that implements the X86 backend.
38 TargetMachine *llvm::allocateX86TargetMachine(const Module &M) {
39 return new X86TargetMachine(M);
43 /// X86TargetMachine ctor - Create an ILP32 architecture model
45 X86TargetMachine::X86TargetMachine(const Module &M)
46 : TargetMachine("X86", true, 4, 4, 4, 4, 4),
47 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4),
52 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
53 // does to emit statically compiled machine code.
54 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
56 // FIXME: Implement the switch instruction in the instruction selector!
57 PM.add(createLowerSwitchPass());
59 // FIXME: Implement the invoke/unwind instructions!
60 PM.add(createLowerInvokePass());
62 // FIXME: The code generator does not properly handle functions with
63 // unreachable basic blocks.
64 PM.add(createCFGSimplificationPass());
67 PM.add(createX86SimpleInstructionSelector(*this));
69 PM.add(createX86PatternInstructionSelector(*this));
71 // Run optional SSA-based machine code optimizations next...
73 PM.add(createX86SSAPeepholeOptimizerPass());
75 // Print the instruction selected machine code...
77 PM.add(createMachineFunctionPrinterPass());
79 // kill floating point registers at the end of basic blocks. this is
80 // done because the floating point register stackifier cannot handle
81 // floating point regs that are live across basic blocks.
82 PM.add(createX86FloatingPointKillerPass());
84 // Perform register allocation to convert to a concrete x86 representation
85 PM.add(createRegisterAllocator());
88 PM.add(createMachineFunctionPrinterPass());
90 PM.add(createX86FloatingPointStackifierPass());
93 PM.add(createMachineFunctionPrinterPass());
95 // Insert prolog/epilog code. Eliminate abstract frame index references...
96 PM.add(createPrologEpilogCodeInserter());
98 PM.add(createX86PeepholeOptimizerPass());
100 if (PrintCode) // Print the register-allocated code
101 PM.add(createX86CodePrinterPass(std::cerr, *this));
103 PM.add(createX86CodePrinterPass(Out, *this));
104 return false; // success!
107 /// addPassesToJITCompile - Add passes to the specified pass manager to
108 /// implement a fast dynamic compiler for this target. Return true if this is
109 /// not supported for this target.
111 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
112 // FIXME: Implement the switch instruction in the instruction selector!
113 PM.add(createLowerSwitchPass());
115 // FIXME: Implement the invoke/unwind instructions!
116 PM.add(createLowerInvokePass());
118 // FIXME: The code generator does not properly handle functions with
119 // unreachable basic blocks.
120 PM.add(createCFGSimplificationPass());
123 PM.add(createX86SimpleInstructionSelector(TM));
125 PM.add(createX86PatternInstructionSelector(TM));
127 // Run optional SSA-based machine code optimizations next...
129 PM.add(createX86SSAPeepholeOptimizerPass());
131 // FIXME: Add SSA based peephole optimizer here.
133 // Print the instruction selected machine code...
135 PM.add(createMachineFunctionPrinterPass());
137 // kill floating point registers at the end of basic blocks. this is
138 // done because the floating point register stackifier cannot handle
139 // floating point regs that are live across basic blocks.
140 PM.add(createX86FloatingPointKillerPass());
142 // Perform register allocation to convert to a concrete x86 representation
143 PM.add(createRegisterAllocator());
146 PM.add(createMachineFunctionPrinterPass());
148 PM.add(createX86FloatingPointStackifierPass());
151 PM.add(createMachineFunctionPrinterPass());
153 // Insert prolog/epilog code. Eliminate abstract frame index references...
154 PM.add(createPrologEpilogCodeInserter());
156 PM.add(createX86PeepholeOptimizerPass());
158 if (PrintCode) // Print the register-allocated code
159 PM.add(createX86CodePrinterPass(std::cerr, TM));