1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Support/TargetRegistry.h"
25 extern "C" void LLVMInitializeX86Target() {
26 // Register the target.
27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 void X86_32TargetMachine::anchor() { }
33 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
34 StringRef CPU, StringRef FS,
35 const TargetOptions &Options,
36 Reloc::Model RM, CodeModel::Model CM,
38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
39 DataLayout(getSubtargetImpl()->isTargetDarwin() ?
40 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
42 (getSubtargetImpl()->isTargetCygMing() ||
43 getSubtargetImpl()->isTargetWindows()) ?
44 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
46 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
54 void X86_64TargetMachine::anchor() { }
56 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
57 StringRef CPU, StringRef FS,
58 const TargetOptions &Options,
59 Reloc::Model RM, CodeModel::Model CM,
61 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
62 DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
70 /// X86TargetMachine ctor - Create an X86 target.
72 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
78 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
79 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
80 FrameLowering(*this, Subtarget),
81 ELFWriterInfo(is64Bit, true) {
82 // Determine the PICStyle based on the target selected.
83 if (getRelocationModel() == Reloc::Static) {
84 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
85 Subtarget.setPICStyle(PICStyles::None);
86 } else if (Subtarget.is64Bit()) {
87 // PIC in 64 bit mode is always rip-rel.
88 Subtarget.setPICStyle(PICStyles::RIPRel);
89 } else if (Subtarget.isTargetCygMing()) {
90 Subtarget.setPICStyle(PICStyles::None);
91 } else if (Subtarget.isTargetDarwin()) {
92 if (getRelocationModel() == Reloc::PIC_)
93 Subtarget.setPICStyle(PICStyles::StubPIC);
95 assert(getRelocationModel() == Reloc::DynamicNoPIC);
96 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
98 } else if (Subtarget.isTargetELF()) {
99 Subtarget.setPICStyle(PICStyles::GOT);
102 // default to hard float ABI
103 if (Options.FloatABIType == FloatABI::Default)
104 this->Options.FloatABIType = FloatABI::Hard;
107 //===----------------------------------------------------------------------===//
108 // Command line options for x86
109 //===----------------------------------------------------------------------===//
111 UseVZeroUpper("x86-use-vzeroupper",
112 cl::desc("Minimize AVX to SSE transition penalty"),
115 //===----------------------------------------------------------------------===//
116 // Pass Pipeline Configuration
117 //===----------------------------------------------------------------------===//
119 bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
120 // Install an instruction selector.
121 PM.add(createX86ISelDag(*this, getOptLevel()));
123 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
124 if (!Subtarget.is64Bit())
125 PM.add(createGlobalBaseRegPass());
130 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
131 PM.add(createX86MaxStackAlignmentHeuristicPass());
132 return false; // -print-machineinstr shouldn't print after this.
135 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
136 PM.add(createX86FloatingPointStackifierPass());
137 return true; // -print-machineinstr should print after this.
140 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
141 bool ShouldPrint = false;
142 if (getOptLevel() != CodeGenOpt::None && Subtarget.hasSSE2()) {
143 PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
147 if (Subtarget.hasAVX() && UseVZeroUpper) {
148 PM.add(createX86IssueVZeroUpperPass());
155 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
156 JITCodeEmitter &JCE) {
157 PM.add(createX86JITCodeEmitterPass(*this, JCE));