1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
25 extern "C" void LLVMInitializeX86Target() {
26 // Register the target.
27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 void X86_32TargetMachine::anchor() { }
33 static std::string computeDataLayout(const X86Subtarget &ST) {
34 // X86 is little endian
35 std::string Ret = "e";
37 // X86 and x32 have 32 bit pointers.
38 if (ST.isTarget64BitILP32() || !ST.is64Bit())
41 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
42 if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
48 // Some ABIs align long double to 128 bits, others to 32.
49 if (ST.isTargetNaCl())
51 else if (ST.is64Bit() || ST.isTargetDarwin())
56 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
58 Ret += "-n8:16:32:64";
62 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
63 if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
71 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
72 StringRef CPU, StringRef FS,
73 const TargetOptions &Options,
74 Reloc::Model RM, CodeModel::Model CM,
76 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
77 DL(computeDataLayout(*getSubtargetImpl())),
85 void X86_64TargetMachine::anchor() { }
87 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
88 StringRef CPU, StringRef FS,
89 const TargetOptions &Options,
90 Reloc::Model RM, CodeModel::Model CM,
92 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
93 // The x32 ABI dictates the ILP32 programming model for x64.
94 DL(computeDataLayout(*getSubtargetImpl())),
102 /// X86TargetMachine ctor - Create an X86 target.
104 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
105 StringRef CPU, StringRef FS,
106 const TargetOptions &Options,
107 Reloc::Model RM, CodeModel::Model CM,
108 CodeGenOpt::Level OL,
110 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
111 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
112 FrameLowering(*this, Subtarget),
113 InstrItins(Subtarget.getInstrItineraryData()){
114 // Determine the PICStyle based on the target selected.
115 if (getRelocationModel() == Reloc::Static) {
116 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
117 Subtarget.setPICStyle(PICStyles::None);
118 } else if (Subtarget.is64Bit()) {
119 // PIC in 64 bit mode is always rip-rel.
120 Subtarget.setPICStyle(PICStyles::RIPRel);
121 } else if (Subtarget.isTargetCOFF()) {
122 Subtarget.setPICStyle(PICStyles::None);
123 } else if (Subtarget.isTargetDarwin()) {
124 if (getRelocationModel() == Reloc::PIC_)
125 Subtarget.setPICStyle(PICStyles::StubPIC);
127 assert(getRelocationModel() == Reloc::DynamicNoPIC);
128 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
130 } else if (Subtarget.isTargetELF()) {
131 Subtarget.setPICStyle(PICStyles::GOT);
134 // default to hard float ABI
135 if (Options.FloatABIType == FloatABI::Default)
136 this->Options.FloatABIType = FloatABI::Hard;
139 //===----------------------------------------------------------------------===//
140 // Command line options for x86
141 //===----------------------------------------------------------------------===//
143 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
144 cl::desc("Minimize AVX to SSE transition penalty"),
147 // Temporary option to control early if-conversion for x86 while adding machine
150 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
151 cl::desc("Enable early if-conversion on X86"));
153 //===----------------------------------------------------------------------===//
154 // X86 Analysis Pass Setup
155 //===----------------------------------------------------------------------===//
157 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
158 // Add first the target-independent BasicTTI pass, then our X86 pass. This
159 // allows the X86 pass to delegate to the target independent layer when
161 PM.add(createBasicTargetTransformInfoPass(this));
162 PM.add(createX86TargetTransformInfoPass(this));
166 //===----------------------------------------------------------------------===//
167 // Pass Pipeline Configuration
168 //===----------------------------------------------------------------------===//
171 /// X86 Code Generator Pass Configuration Options.
172 class X86PassConfig : public TargetPassConfig {
174 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
175 : TargetPassConfig(TM, PM) {}
177 X86TargetMachine &getX86TargetMachine() const {
178 return getTM<X86TargetMachine>();
181 const X86Subtarget &getX86Subtarget() const {
182 return *getX86TargetMachine().getSubtargetImpl();
185 virtual bool addInstSelector();
186 virtual bool addILPOpts();
187 virtual bool addPreRegAlloc();
188 virtual bool addPostRegAlloc();
189 virtual bool addPreEmitPass();
193 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
194 return new X86PassConfig(this, PM);
197 bool X86PassConfig::addInstSelector() {
198 // Install an instruction selector.
199 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
201 // For ELF, cleanup any local-dynamic TLS accesses.
202 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
203 addPass(createCleanupLocalDynamicTLSPass());
205 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
206 if (!getX86Subtarget().is64Bit())
207 addPass(createGlobalBaseRegPass());
212 bool X86PassConfig::addILPOpts() {
213 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
214 addPass(&EarlyIfConverterID);
220 bool X86PassConfig::addPreRegAlloc() {
221 return false; // -print-machineinstr shouldn't print after this.
224 bool X86PassConfig::addPostRegAlloc() {
225 addPass(createX86FloatingPointStackifierPass());
226 return true; // -print-machineinstr should print after this.
229 bool X86PassConfig::addPreEmitPass() {
230 bool ShouldPrint = false;
231 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
232 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
236 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
237 addPass(createX86IssueVZeroUpperPass());
241 if (getOptLevel() != CodeGenOpt::None &&
242 getX86Subtarget().padShortFunctions()) {
243 addPass(createX86PadShortFunctions());
246 if (getOptLevel() != CodeGenOpt::None &&
247 getX86Subtarget().LEAusesAG()){
248 addPass(createX86FixupLEAs());
255 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
256 JITCodeEmitter &JCE) {
257 PM.add(createX86JITCodeEmitterPass(*this, JCE));