1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/ADT/Statistic.h"
28 X86VectorEnum llvm::X86Vector = NoSSE;
31 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
32 cl::desc("Disable the ssa-based peephole optimizer "
33 "(defaults to disabled)"));
34 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
35 cl::desc("Disable the X86 asm printer, for use "
36 "when profiling the code generator."));
38 // FIXME: This should eventually be handled with target triples and
40 cl::opt<X86VectorEnum, true>
42 cl::desc("Enable SSE support in the X86 target:"),
44 clEnumValN(SSE, "sse", " Enable SSE support"),
45 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
46 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
48 cl::location(X86Vector), cl::init(NoSSE));
50 // Register the target.
51 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
54 unsigned X86TargetMachine::getJITMatchQuality() {
55 #if defined(i386) || defined(__i386__) || defined(__x86__)
62 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
63 if (M.getEndianness() == Module::LittleEndian &&
64 M.getPointerSize() == Module::Pointer32)
65 return 10; // Direct match
66 else if (M.getEndianness() != Module::AnyEndianness ||
67 M.getPointerSize() != Module::AnyPointerSize)
68 return 0; // Match for some other target
70 return getJITMatchQuality()/2;
73 /// X86TargetMachine ctor - Create an ILP32 architecture model
75 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
76 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
77 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, -4),
82 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
83 // does to emit statically compiled machine code.
84 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
86 // FIXME: Implement efficient support for garbage collection intrinsics.
87 PM.add(createLowerGCPass());
89 // FIXME: Implement the invoke/unwind instructions!
90 PM.add(createLowerInvokePass());
92 // FIXME: Implement the switch instruction in the instruction selector!
93 PM.add(createLowerSwitchPass());
95 // Make sure that no unreachable blocks are instruction selected.
96 PM.add(createUnreachableBlockEliminationPass());
98 PM.add(createX86SimpleInstructionSelector(*this));
100 // Run optional SSA-based machine code optimizations next...
102 PM.add(createX86SSAPeepholeOptimizerPass());
104 // Print the instruction selected machine code...
105 if (PrintMachineCode)
106 PM.add(createMachineFunctionPrinterPass(&std::cerr));
108 // Perform register allocation to convert to a concrete x86 representation
109 PM.add(createRegisterAllocator());
111 if (PrintMachineCode)
112 PM.add(createMachineFunctionPrinterPass(&std::cerr));
114 PM.add(createX86FloatingPointStackifierPass());
116 if (PrintMachineCode)
117 PM.add(createMachineFunctionPrinterPass(&std::cerr));
119 // Insert prolog/epilog code. Eliminate abstract frame index references...
120 PM.add(createPrologEpilogCodeInserter());
122 PM.add(createX86PeepholeOptimizerPass());
124 if (PrintMachineCode) // Print the register-allocated code
125 PM.add(createX86CodePrinterPass(std::cerr, *this));
128 PM.add(createX86CodePrinterPass(Out, *this));
130 // Delete machine code for this function
131 PM.add(createMachineCodeDeleter());
133 return false; // success!
136 /// addPassesToJITCompile - Add passes to the specified pass manager to
137 /// implement a fast dynamic compiler for this target. Return true if this is
138 /// not supported for this target.
140 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
141 // FIXME: Implement efficient support for garbage collection intrinsics.
142 PM.add(createLowerGCPass());
144 // FIXME: Implement the invoke/unwind instructions!
145 PM.add(createLowerInvokePass());
147 // FIXME: Implement the switch instruction in the instruction selector!
148 PM.add(createLowerSwitchPass());
150 // Make sure that no unreachable blocks are instruction selected.
151 PM.add(createUnreachableBlockEliminationPass());
153 PM.add(createX86SimpleInstructionSelector(TM));
155 // Run optional SSA-based machine code optimizations next...
157 PM.add(createX86SSAPeepholeOptimizerPass());
159 // FIXME: Add SSA based peephole optimizer here.
161 // Print the instruction selected machine code...
162 if (PrintMachineCode)
163 PM.add(createMachineFunctionPrinterPass(&std::cerr));
165 // Perform register allocation to convert to a concrete x86 representation
166 PM.add(createRegisterAllocator());
168 if (PrintMachineCode)
169 PM.add(createMachineFunctionPrinterPass(&std::cerr));
171 PM.add(createX86FloatingPointStackifierPass());
173 if (PrintMachineCode)
174 PM.add(createMachineFunctionPrinterPass(&std::cerr));
176 // Insert prolog/epilog code. Eliminate abstract frame index references...
177 PM.add(createPrologEpilogCodeInserter());
179 PM.add(createX86PeepholeOptimizerPass());
181 if (PrintMachineCode) // Print the register-allocated code
182 PM.add(createX86CodePrinterPass(std::cerr, TM));