1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/ADT/Statistic.h"
28 X86VectorEnum llvm::X86Vector = NoSSE;
29 bool llvm::X86ScalarSSE = false;
30 bool llvm::X86DAGIsel = false;
32 /// X86TargetMachineModule - Note that this is used on hosts that cannot link
33 /// in a library unless there are references into the library. In particular,
34 /// it seems that it is not possible to get things to work on Win32 without
35 /// this. Though it is unused, do not remove it.
36 extern "C" int X86TargetMachineModule;
37 int X86TargetMachineModule = 0;
40 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
41 cl::desc("Disable the X86 asm printer, for use "
42 "when profiling the code generator."));
43 cl::opt<bool, true> EnableSSEFP("enable-sse-scalar-fp",
44 cl::desc("Perform FP math in SSE regs instead of the FP stack"),
45 cl::location(X86ScalarSSE),
48 cl::opt<bool, true> EnableX86DAGDAG("enable-x86-dag-isel", cl::Hidden,
49 cl::desc("Enable DAG-to-DAG isel for X86"),
50 cl::location(X86DAGIsel),
53 // FIXME: This should eventually be handled with target triples and
55 cl::opt<X86VectorEnum, true>
57 cl::desc("Enable SSE support in the X86 target:"),
59 clEnumValN(SSE, "sse", " Enable SSE support"),
60 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
61 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
63 cl::location(X86Vector), cl::init(NoSSE));
65 // Register the target.
66 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
69 unsigned X86TargetMachine::getJITMatchQuality() {
70 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
77 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
78 // We strongly match "i[3-9]86-*".
79 std::string TT = M.getTargetTriple();
80 if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
81 TT[4] == '-' && TT[1] - '3' < 6)
84 if (M.getEndianness() == Module::LittleEndian &&
85 M.getPointerSize() == Module::Pointer32)
86 return 10; // Weak match
87 else if (M.getEndianness() != Module::AnyEndianness ||
88 M.getPointerSize() != Module::AnyPointerSize)
89 return 0; // Match for some other target
91 return getJITMatchQuality()/2;
94 /// X86TargetMachine ctor - Create an ILP32 architecture model
96 X86TargetMachine::X86TargetMachine(const Module &M,
97 IntrinsicLowering *IL,
98 const std::string &FS)
99 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
101 FrameInfo(TargetFrameInfo::StackGrowsDown,
102 Subtarget.getStackAlignment(), -4),
104 // Scalar SSE FP requires at least SSE2
105 X86ScalarSSE &= X86Vector >= SSE2;
109 // addPassesToEmitFile - We currently use all of the same passes as the JIT
110 // does to emit statically compiled machine code.
111 bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
112 CodeGenFileType FileType,
114 if (FileType != TargetMachine::AssemblyFile &&
115 FileType != TargetMachine::ObjectFile) return true;
117 // FIXME: Implement efficient support for garbage collection intrinsics.
118 PM.add(createLowerGCPass());
120 // FIXME: Implement the invoke/unwind instructions!
121 PM.add(createLowerInvokePass());
123 // FIXME: Implement the switch instruction in the instruction selector!
124 PM.add(createLowerSwitchPass());
126 // Make sure that no unreachable blocks are instruction selected.
127 PM.add(createUnreachableBlockEliminationPass());
129 // Install an instruction selector.
131 PM.add(createX86ISelDag(*this));
133 PM.add(createX86ISelPattern(*this));
135 // Print the instruction selected machine code...
136 if (PrintMachineCode)
137 PM.add(createMachineFunctionPrinterPass(&std::cerr));
139 // Perform register allocation to convert to a concrete x86 representation
140 PM.add(createRegisterAllocator());
142 if (PrintMachineCode)
143 PM.add(createMachineFunctionPrinterPass(&std::cerr));
145 PM.add(createX86FloatingPointStackifierPass());
147 if (PrintMachineCode)
148 PM.add(createMachineFunctionPrinterPass(&std::cerr));
150 // Insert prolog/epilog code. Eliminate abstract frame index references...
151 PM.add(createPrologEpilogCodeInserter());
153 PM.add(createX86PeepholeOptimizerPass());
155 if (PrintMachineCode) // Print the register-allocated code
156 PM.add(createX86CodePrinterPass(std::cerr, *this));
161 assert(0 && "Unexpected filetype here!");
162 case TargetMachine::AssemblyFile:
163 PM.add(createX86CodePrinterPass(Out, *this));
165 case TargetMachine::ObjectFile:
166 // FIXME: We only support emission of ELF files for now, this should check
167 // the target triple and decide on the format to write (e.g. COFF on
169 addX86ELFObjectWriterPass(PM, Out, *this);
173 // Delete machine code for this function
174 PM.add(createMachineCodeDeleter());
176 return false; // success!
179 /// addPassesToJITCompile - Add passes to the specified pass manager to
180 /// implement a fast dynamic compiler for this target. Return true if this is
181 /// not supported for this target.
183 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
184 // FIXME: Implement efficient support for garbage collection intrinsics.
185 PM.add(createLowerGCPass());
187 // FIXME: Implement the invoke/unwind instructions!
188 PM.add(createLowerInvokePass());
190 // FIXME: Implement the switch instruction in the instruction selector!
191 PM.add(createLowerSwitchPass());
193 // Make sure that no unreachable blocks are instruction selected.
194 PM.add(createUnreachableBlockEliminationPass());
196 // Install an instruction selector.
198 PM.add(createX86ISelDag(TM));
200 PM.add(createX86ISelPattern(TM));
202 // FIXME: Add SSA based peephole optimizer here.
204 // Print the instruction selected machine code...
205 if (PrintMachineCode)
206 PM.add(createMachineFunctionPrinterPass(&std::cerr));
208 // Perform register allocation to convert to a concrete x86 representation
209 PM.add(createRegisterAllocator());
211 if (PrintMachineCode)
212 PM.add(createMachineFunctionPrinterPass(&std::cerr));
214 PM.add(createX86FloatingPointStackifierPass());
216 if (PrintMachineCode)
217 PM.add(createMachineFunctionPrinterPass(&std::cerr));
219 // Insert prolog/epilog code. Eliminate abstract frame index references...
220 PM.add(createPrologEpilogCodeInserter());
222 PM.add(createX86PeepholeOptimizerPass());
224 if (PrintMachineCode) // Print the register-allocated code
225 PM.add(createX86CodePrinterPass(std::cerr, TM));
228 bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
229 MachineCodeEmitter &MCE) {
230 PM.add(createX86CodeEmitterPass(MCE));
231 // Delete machine code for this function
232 PM.add(createMachineCodeDeleter());