1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
25 extern "C" void LLVMInitializeX86Target() {
26 // Register the target.
27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 void X86_32TargetMachine::anchor() { }
33 static std::string computeDataLayout(const X86Subtarget &ST) {
34 // X86 is little endian
35 std::string Ret = "e";
37 // X86 and x32 have 32 bit pointers, x86-64 has 64 bit pointers
38 if (ST.isTarget64BitILP32() || !ST.is64Bit())
43 // Objects on the stack ore aligned to 64 bits.
44 // FIXME: of any size?
48 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
49 if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
50 Ret += "-f64:64:64-i64:64:64";
52 Ret += "-f64:32:64-i64:32:64";
54 // Some ABIs align long double to 128 bits, others to 32.
55 if (ST.is64Bit() || ST.isTargetDarwin())
56 Ret += "-f80:128:128";
60 // 128 bit floats (?) are aligned to 128 bits.
61 Ret += "-f128:128:128";
63 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
65 Ret += "-n8:16:32:64";
69 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
70 if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
78 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
79 StringRef CPU, StringRef FS,
80 const TargetOptions &Options,
81 Reloc::Model RM, CodeModel::Model CM,
83 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
84 DL(computeDataLayout(*getSubtargetImpl())),
92 void X86_64TargetMachine::anchor() { }
94 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
95 StringRef CPU, StringRef FS,
96 const TargetOptions &Options,
97 Reloc::Model RM, CodeModel::Model CM,
99 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
100 // The x32 ABI dictates the ILP32 programming model for x64.
101 DL(computeDataLayout(*getSubtargetImpl())),
109 /// X86TargetMachine ctor - Create an X86 target.
111 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
112 StringRef CPU, StringRef FS,
113 const TargetOptions &Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL,
117 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
118 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
119 FrameLowering(*this, Subtarget),
120 InstrItins(Subtarget.getInstrItineraryData()){
121 // Determine the PICStyle based on the target selected.
122 if (getRelocationModel() == Reloc::Static) {
123 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
124 Subtarget.setPICStyle(PICStyles::None);
125 } else if (Subtarget.is64Bit()) {
126 // PIC in 64 bit mode is always rip-rel.
127 Subtarget.setPICStyle(PICStyles::RIPRel);
128 } else if (Subtarget.isTargetCOFF()) {
129 Subtarget.setPICStyle(PICStyles::None);
130 } else if (Subtarget.isTargetDarwin()) {
131 if (getRelocationModel() == Reloc::PIC_)
132 Subtarget.setPICStyle(PICStyles::StubPIC);
134 assert(getRelocationModel() == Reloc::DynamicNoPIC);
135 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
137 } else if (Subtarget.isTargetELF()) {
138 Subtarget.setPICStyle(PICStyles::GOT);
141 // default to hard float ABI
142 if (Options.FloatABIType == FloatABI::Default)
143 this->Options.FloatABIType = FloatABI::Hard;
146 //===----------------------------------------------------------------------===//
147 // Command line options for x86
148 //===----------------------------------------------------------------------===//
150 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
151 cl::desc("Minimize AVX to SSE transition penalty"),
154 // Temporary option to control early if-conversion for x86 while adding machine
157 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
158 cl::desc("Enable early if-conversion on X86"));
160 //===----------------------------------------------------------------------===//
161 // X86 Analysis Pass Setup
162 //===----------------------------------------------------------------------===//
164 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
165 // Add first the target-independent BasicTTI pass, then our X86 pass. This
166 // allows the X86 pass to delegate to the target independent layer when
168 PM.add(createBasicTargetTransformInfoPass(this));
169 PM.add(createX86TargetTransformInfoPass(this));
173 //===----------------------------------------------------------------------===//
174 // Pass Pipeline Configuration
175 //===----------------------------------------------------------------------===//
178 /// X86 Code Generator Pass Configuration Options.
179 class X86PassConfig : public TargetPassConfig {
181 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
182 : TargetPassConfig(TM, PM) {}
184 X86TargetMachine &getX86TargetMachine() const {
185 return getTM<X86TargetMachine>();
188 const X86Subtarget &getX86Subtarget() const {
189 return *getX86TargetMachine().getSubtargetImpl();
192 virtual bool addInstSelector();
193 virtual bool addILPOpts();
194 virtual bool addPreRegAlloc();
195 virtual bool addPostRegAlloc();
196 virtual bool addPreEmitPass();
200 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
201 return new X86PassConfig(this, PM);
204 bool X86PassConfig::addInstSelector() {
205 // Install an instruction selector.
206 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
208 // For ELF, cleanup any local-dynamic TLS accesses.
209 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
210 addPass(createCleanupLocalDynamicTLSPass());
212 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
213 if (!getX86Subtarget().is64Bit())
214 addPass(createGlobalBaseRegPass());
219 bool X86PassConfig::addILPOpts() {
220 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
221 addPass(&EarlyIfConverterID);
227 bool X86PassConfig::addPreRegAlloc() {
228 return false; // -print-machineinstr shouldn't print after this.
231 bool X86PassConfig::addPostRegAlloc() {
232 addPass(createX86FloatingPointStackifierPass());
233 return true; // -print-machineinstr should print after this.
236 bool X86PassConfig::addPreEmitPass() {
237 bool ShouldPrint = false;
238 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
239 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
243 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
244 addPass(createX86IssueVZeroUpperPass());
248 if (getOptLevel() != CodeGenOpt::None &&
249 getX86Subtarget().padShortFunctions()) {
250 addPass(createX86PadShortFunctions());
253 if (getOptLevel() != CodeGenOpt::None &&
254 getX86Subtarget().LEAusesAG()){
255 addPass(createX86FixupLEAs());
262 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
263 JITCodeEmitter &JCE) {
264 PM.add(createX86JITCodeEmitterPass(*this, JCE));