1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetRegistry.h"
24 extern "C" void LLVMInitializeX86Target() {
25 // Register the target.
26 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
27 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
32 StringRef CPU, StringRef FS,
33 Reloc::Model RM, CodeModel::Model CM)
34 : X86TargetMachine(T, TT, CPU, FS, RM, CM, false),
35 DataLayout(getSubtargetImpl()->isTargetDarwin() ?
36 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" :
37 (getSubtargetImpl()->isTargetCygMing() ||
38 getSubtargetImpl()->isTargetWindows()) ?
39 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-n8:16:32" :
40 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-n8:16:32"),
48 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
49 StringRef CPU, StringRef FS,
50 Reloc::Model RM, CodeModel::Model CM)
51 : X86TargetMachine(T, TT, CPU, FS, RM, CM, true),
52 DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"),
59 /// X86TargetMachine ctor - Create an X86 target.
61 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
62 StringRef CPU, StringRef FS,
63 Reloc::Model RM, CodeModel::Model CM,
65 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
66 Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
67 FrameLowering(*this, Subtarget),
68 ELFWriterInfo(is64Bit, true) {
69 // Determine the PICStyle based on the target selected.
70 if (getRelocationModel() == Reloc::Static) {
71 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
72 Subtarget.setPICStyle(PICStyles::None);
73 } else if (Subtarget.is64Bit()) {
74 // PIC in 64 bit mode is always rip-rel.
75 Subtarget.setPICStyle(PICStyles::RIPRel);
76 } else if (Subtarget.isTargetCygMing()) {
77 Subtarget.setPICStyle(PICStyles::None);
78 } else if (Subtarget.isTargetDarwin()) {
79 if (getRelocationModel() == Reloc::PIC_)
80 Subtarget.setPICStyle(PICStyles::StubPIC);
82 assert(getRelocationModel() == Reloc::DynamicNoPIC);
83 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
85 } else if (Subtarget.isTargetELF()) {
86 Subtarget.setPICStyle(PICStyles::GOT);
89 // default to hard float ABI
90 if (FloatABIType == FloatABI::Default)
91 FloatABIType = FloatABI::Hard;
94 //===----------------------------------------------------------------------===//
95 // Pass Pipeline Configuration
96 //===----------------------------------------------------------------------===//
98 bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
99 CodeGenOpt::Level OptLevel) {
100 // Install an instruction selector.
101 PM.add(createX86ISelDag(*this, OptLevel));
103 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
104 if (!Subtarget.is64Bit())
105 PM.add(createGlobalBaseRegPass());
110 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
111 CodeGenOpt::Level OptLevel) {
112 PM.add(createX86MaxStackAlignmentHeuristicPass());
113 return false; // -print-machineinstr shouldn't print after this.
116 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
117 CodeGenOpt::Level OptLevel) {
118 PM.add(createX86FloatingPointStackifierPass());
119 return true; // -print-machineinstr should print after this.
122 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
123 CodeGenOpt::Level OptLevel) {
124 if (OptLevel != CodeGenOpt::None && Subtarget.hasSSE2()) {
125 PM.add(createSSEDomainFixPass());
131 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
132 CodeGenOpt::Level OptLevel,
133 JITCodeEmitter &JCE) {
134 PM.add(createX86JITCodeEmitterPass(*this, JCE));