1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetMachineImpls.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "Support/CommandLine.h"
25 #include "Support/Statistic.h"
29 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
30 cl::desc("Use the 'simple' X86 instruction selector"));
31 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
32 cl::desc("Disable the ssa-based peephole optimizer "
33 "(defaults to disabled)"));
34 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
35 cl::desc("Disable the X86 asm printer, for use "
36 "when profiling the code generator."));
37 cl::opt<bool> NoSimpleISel("disable-simple-isel", cl::init(true),
38 cl::desc("Use the hand coded 'simple' X86 instruction selector"));
40 // Register the target.
41 RegisterTarget<X86TargetMachine> X("x86", "IA-32 (Pentium and above)");
44 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
45 // that implements the X86 backend.
47 TargetMachine *llvm::allocateX86TargetMachine(const Module &M,
48 IntrinsicLowering *IL) {
49 return new X86TargetMachine(M, IL);
52 unsigned X86TargetMachine::getJITMatchQuality() {
53 #if defined(i386) || defined(__i386__) || defined(__x86__)
60 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
61 if (M.getEndianness() == Module::LittleEndian &&
62 M.getPointerSize() == Module::Pointer32)
63 return 10; // Direct match
64 else if (M.getEndianness() != Module::AnyEndianness ||
65 M.getPointerSize() != Module::AnyPointerSize)
66 return 0; // Match for some other target
68 return getJITMatchQuality()/2;
71 /// X86TargetMachine ctor - Create an ILP32 architecture model
73 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
74 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
75 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, -4),
80 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
81 // does to emit statically compiled machine code.
82 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
84 // FIXME: Implement efficient support for garbage collection intrinsics.
85 PM.add(createLowerGCPass());
87 // FIXME: Implement the invoke/unwind instructions!
88 PM.add(createLowerInvokePass());
90 // FIXME: Implement the switch instruction in the instruction selector!
91 PM.add(createLowerSwitchPass());
93 // Make sure that no unreachable blocks are instruction selected.
94 PM.add(createUnreachableBlockEliminationPass());
96 if (NoPatternISel && NoSimpleISel)
97 PM.add(createX86SimpleInstructionSelector(*this));
98 else if (NoPatternISel)
99 PM.add(createX86ReallySimpleInstructionSelector(*this));
101 PM.add(createX86PatternInstructionSelector(*this));
103 // Run optional SSA-based machine code optimizations next...
105 PM.add(createX86SSAPeepholeOptimizerPass());
107 // Print the instruction selected machine code...
108 if (PrintMachineCode)
109 PM.add(createMachineFunctionPrinterPass(&std::cerr));
111 // Perform register allocation to convert to a concrete x86 representation
112 PM.add(createRegisterAllocator());
114 if (PrintMachineCode)
115 PM.add(createMachineFunctionPrinterPass(&std::cerr));
117 PM.add(createX86FloatingPointStackifierPass());
119 if (PrintMachineCode)
120 PM.add(createMachineFunctionPrinterPass(&std::cerr));
122 // Insert prolog/epilog code. Eliminate abstract frame index references...
123 PM.add(createPrologEpilogCodeInserter());
125 PM.add(createX86PeepholeOptimizerPass());
127 if (PrintMachineCode) // Print the register-allocated code
128 PM.add(createX86CodePrinterPass(std::cerr, *this));
131 PM.add(createX86CodePrinterPass(Out, *this));
133 // Delete machine code for this function
134 PM.add(createMachineCodeDeleter());
136 return false; // success!
139 /// addPassesToJITCompile - Add passes to the specified pass manager to
140 /// implement a fast dynamic compiler for this target. Return true if this is
141 /// not supported for this target.
143 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
144 // FIXME: Implement efficient support for garbage collection intrinsics.
145 PM.add(createLowerGCPass());
147 // FIXME: Implement the invoke/unwind instructions!
148 PM.add(createLowerInvokePass());
150 // FIXME: Implement the switch instruction in the instruction selector!
151 PM.add(createLowerSwitchPass());
153 // Make sure that no unreachable blocks are instruction selected.
154 PM.add(createUnreachableBlockEliminationPass());
157 PM.add(createX86SimpleInstructionSelector(TM));
159 PM.add(createX86PatternInstructionSelector(TM));
161 // Run optional SSA-based machine code optimizations next...
163 PM.add(createX86SSAPeepholeOptimizerPass());
165 // FIXME: Add SSA based peephole optimizer here.
167 // Print the instruction selected machine code...
168 if (PrintMachineCode)
169 PM.add(createMachineFunctionPrinterPass(&std::cerr));
171 // Perform register allocation to convert to a concrete x86 representation
172 PM.add(createRegisterAllocator());
174 if (PrintMachineCode)
175 PM.add(createMachineFunctionPrinterPass(&std::cerr));
177 PM.add(createX86FloatingPointStackifierPass());
179 if (PrintMachineCode)
180 PM.add(createMachineFunctionPrinterPass(&std::cerr));
182 // Insert prolog/epilog code. Eliminate abstract frame index references...
183 PM.add(createPrologEpilogCodeInserter());
185 PM.add(createX86PeepholeOptimizerPass());
187 if (PrintMachineCode) // Print the register-allocated code
188 PM.add(createX86CodePrinterPass(std::cerr, TM));