1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include "llvm/Target/TargetOptions.h"
24 extern "C" void LLVMInitializeX86Target() {
25 // Register the target.
26 RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
27 RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
30 void X86TargetMachine::anchor() { }
32 static std::string computeDataLayout(const X86Subtarget &ST) {
33 // X86 is little endian
34 std::string Ret = "e";
36 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
37 // X86 and x32 have 32 bit pointers.
38 if (ST.isTarget64BitILP32() || !ST.is64Bit())
41 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
42 if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC() ||
48 // Some ABIs align long double to 128 bits, others to 32.
49 if (ST.isTargetNaCl())
51 else if (ST.is64Bit() || ST.isTargetDarwin())
56 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
58 Ret += "-n8:16:32:64";
62 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
63 if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetKnownWindowsMSVC()))
71 /// X86TargetMachine ctor - Create an X86 target.
73 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
74 StringRef FS, const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
77 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
78 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride),
79 FrameLowering(TargetFrameLowering::StackGrowsDown,
80 Subtarget.getStackAlignment(),
81 Subtarget.is64Bit() ? -8 : -4),
82 DL(computeDataLayout(*getSubtargetImpl())), InstrInfo(*this),
83 TLInfo(*this), TSInfo(DL), JITInfo(*this) {
84 // Determine the PICStyle based on the target selected.
85 if (getRelocationModel() == Reloc::Static) {
86 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
87 Subtarget.setPICStyle(PICStyles::None);
88 } else if (Subtarget.is64Bit()) {
89 // PIC in 64 bit mode is always rip-rel.
90 Subtarget.setPICStyle(PICStyles::RIPRel);
91 } else if (Subtarget.isTargetCOFF()) {
92 Subtarget.setPICStyle(PICStyles::None);
93 } else if (Subtarget.isTargetDarwin()) {
94 if (getRelocationModel() == Reloc::PIC_)
95 Subtarget.setPICStyle(PICStyles::StubPIC);
97 assert(getRelocationModel() == Reloc::DynamicNoPIC);
98 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
100 } else if (Subtarget.isTargetELF()) {
101 Subtarget.setPICStyle(PICStyles::GOT);
104 // default to hard float ABI
105 if (Options.FloatABIType == FloatABI::Default)
106 this->Options.FloatABIType = FloatABI::Hard;
108 // Windows stack unwinder gets confused when execution flow "falls through"
109 // after a call to 'noreturn' function.
110 // To prevent that, we emit a trap for 'unreachable' IR instructions.
111 // (which on X86, happens to be the 'ud2' instruction)
112 if (Subtarget.isTargetWin64())
113 this->Options.TrapUnreachable = true;
118 //===----------------------------------------------------------------------===//
119 // Command line options for x86
120 //===----------------------------------------------------------------------===//
122 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
123 cl::desc("Minimize AVX to SSE transition penalty"),
126 //===----------------------------------------------------------------------===//
127 // X86 Analysis Pass Setup
128 //===----------------------------------------------------------------------===//
130 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
131 // Add first the target-independent BasicTTI pass, then our X86 pass. This
132 // allows the X86 pass to delegate to the target independent layer when
134 PM.add(createBasicTargetTransformInfoPass(this));
135 PM.add(createX86TargetTransformInfoPass(this));
139 //===----------------------------------------------------------------------===//
140 // Pass Pipeline Configuration
141 //===----------------------------------------------------------------------===//
144 /// X86 Code Generator Pass Configuration Options.
145 class X86PassConfig : public TargetPassConfig {
147 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
148 : TargetPassConfig(TM, PM) {}
150 X86TargetMachine &getX86TargetMachine() const {
151 return getTM<X86TargetMachine>();
154 const X86Subtarget &getX86Subtarget() const {
155 return *getX86TargetMachine().getSubtargetImpl();
158 bool addInstSelector() override;
159 bool addILPOpts() override;
160 bool addPreRegAlloc() override;
161 bool addPostRegAlloc() override;
162 bool addPreEmitPass() override;
166 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
167 return new X86PassConfig(this, PM);
170 bool X86PassConfig::addInstSelector() {
171 // Install an instruction selector.
172 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
174 // For ELF, cleanup any local-dynamic TLS accesses.
175 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
176 addPass(createCleanupLocalDynamicTLSPass());
178 addPass(createX86GlobalBaseRegPass());
183 bool X86PassConfig::addILPOpts() {
184 addPass(&EarlyIfConverterID);
188 bool X86PassConfig::addPreRegAlloc() {
189 return false; // -print-machineinstr shouldn't print after this.
192 bool X86PassConfig::addPostRegAlloc() {
193 addPass(createX86FloatingPointStackifierPass());
194 return true; // -print-machineinstr should print after this.
197 bool X86PassConfig::addPreEmitPass() {
198 bool ShouldPrint = false;
199 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
200 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
205 addPass(createX86IssueVZeroUpperPass());
209 if (getOptLevel() != CodeGenOpt::None) {
210 addPass(createX86PadShortFunctions());
211 addPass(createX86FixupLEAs());
218 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
219 JITCodeEmitter &JCE) {
220 PM.add(createX86JITCodeEmitterPass(*this, JCE));