1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "Support/CommandLine.h"
25 #include "Support/Statistic.h"
29 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
30 cl::desc("Disable the ssa-based peephole optimizer "
31 "(defaults to disabled)"));
32 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
33 cl::desc("Disable the X86 asm printer, for use "
34 "when profiling the code generator."));
36 // Register the target.
37 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
40 unsigned X86TargetMachine::getJITMatchQuality() {
41 #if defined(i386) || defined(__i386__) || defined(__x86__)
48 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
49 if (M.getEndianness() == Module::LittleEndian &&
50 M.getPointerSize() == Module::Pointer32)
51 return 10; // Direct match
52 else if (M.getEndianness() != Module::AnyEndianness ||
53 M.getPointerSize() != Module::AnyPointerSize)
54 return 0; // Match for some other target
56 return getJITMatchQuality()/2;
59 /// X86TargetMachine ctor - Create an ILP32 architecture model
61 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
62 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
63 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, -4),
68 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
69 // does to emit statically compiled machine code.
70 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
72 // FIXME: Implement efficient support for garbage collection intrinsics.
73 PM.add(createLowerGCPass());
75 // FIXME: Implement the invoke/unwind instructions!
76 PM.add(createLowerInvokePass());
78 // FIXME: Implement the switch instruction in the instruction selector!
79 PM.add(createLowerSwitchPass());
81 // Make sure that no unreachable blocks are instruction selected.
82 PM.add(createUnreachableBlockEliminationPass());
84 PM.add(createX86SimpleInstructionSelector(*this));
86 // Run optional SSA-based machine code optimizations next...
88 PM.add(createX86SSAPeepholeOptimizerPass());
90 // Print the instruction selected machine code...
92 PM.add(createMachineFunctionPrinterPass(&std::cerr));
94 // Perform register allocation to convert to a concrete x86 representation
95 PM.add(createRegisterAllocator());
98 PM.add(createMachineFunctionPrinterPass(&std::cerr));
100 PM.add(createX86FloatingPointStackifierPass());
102 if (PrintMachineCode)
103 PM.add(createMachineFunctionPrinterPass(&std::cerr));
105 // Insert prolog/epilog code. Eliminate abstract frame index references...
106 PM.add(createPrologEpilogCodeInserter());
108 PM.add(createX86PeepholeOptimizerPass());
110 if (PrintMachineCode) // Print the register-allocated code
111 PM.add(createX86CodePrinterPass(std::cerr, *this));
114 PM.add(createX86CodePrinterPass(Out, *this));
116 // Delete machine code for this function
117 PM.add(createMachineCodeDeleter());
119 return false; // success!
122 /// addPassesToJITCompile - Add passes to the specified pass manager to
123 /// implement a fast dynamic compiler for this target. Return true if this is
124 /// not supported for this target.
126 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
127 // FIXME: Implement efficient support for garbage collection intrinsics.
128 PM.add(createLowerGCPass());
130 // FIXME: Implement the invoke/unwind instructions!
131 PM.add(createLowerInvokePass());
133 // FIXME: Implement the switch instruction in the instruction selector!
134 PM.add(createLowerSwitchPass());
136 // Make sure that no unreachable blocks are instruction selected.
137 PM.add(createUnreachableBlockEliminationPass());
139 PM.add(createX86SimpleInstructionSelector(TM));
141 // Run optional SSA-based machine code optimizations next...
143 PM.add(createX86SSAPeepholeOptimizerPass());
145 // FIXME: Add SSA based peephole optimizer here.
147 // Print the instruction selected machine code...
148 if (PrintMachineCode)
149 PM.add(createMachineFunctionPrinterPass(&std::cerr));
151 // Perform register allocation to convert to a concrete x86 representation
152 PM.add(createRegisterAllocator());
154 if (PrintMachineCode)
155 PM.add(createMachineFunctionPrinterPass(&std::cerr));
157 PM.add(createX86FloatingPointStackifierPass());
159 if (PrintMachineCode)
160 PM.add(createMachineFunctionPrinterPass(&std::cerr));
162 // Insert prolog/epilog code. Eliminate abstract frame index references...
163 PM.add(createPrologEpilogCodeInserter());
165 PM.add(createX86PeepholeOptimizerPass());
167 if (PrintMachineCode) // Print the register-allocated code
168 PM.add(createX86CodePrinterPass(std::cerr, TM));