1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/IntrinsicLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineImpls.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "Support/CommandLine.h"
24 #include "Support/Statistic.h"
28 cl::opt<bool> PrintCode("print-machineinstrs",
29 cl::desc("Print generated machine code"));
30 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
31 cl::desc("Use the 'simple' X86 instruction selector"));
32 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
33 cl::desc("Disable the ssa-based peephole optimizer "
34 "(defaults to disabled)"));
37 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
38 // that implements the X86 backend.
40 TargetMachine *llvm::allocateX86TargetMachine(const Module &M,
41 IntrinsicLowering *IL) {
42 return new X86TargetMachine(M, IL);
46 /// X86TargetMachine ctor - Create an ILP32 architecture model
48 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *IL)
49 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
50 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4),
55 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
56 // does to emit statically compiled machine code.
57 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
59 // FIXME: Implement the switch instruction in the instruction selector!
60 PM.add(createLowerSwitchPass());
62 // FIXME: Implement the invoke/unwind instructions!
63 PM.add(createLowerInvokePass());
65 // FIXME: The code generator does not properly handle functions with
66 // unreachable basic blocks.
67 PM.add(createCFGSimplificationPass());
70 PM.add(createX86SimpleInstructionSelector(*this));
72 PM.add(createX86PatternInstructionSelector(*this));
74 // Run optional SSA-based machine code optimizations next...
76 PM.add(createX86SSAPeepholeOptimizerPass());
78 // Print the instruction selected machine code...
80 PM.add(createMachineFunctionPrinterPass());
82 // Perform register allocation to convert to a concrete x86 representation
83 PM.add(createRegisterAllocator());
86 PM.add(createMachineFunctionPrinterPass());
88 PM.add(createX86FloatingPointStackifierPass());
91 PM.add(createMachineFunctionPrinterPass());
93 // Insert prolog/epilog code. Eliminate abstract frame index references...
94 PM.add(createPrologEpilogCodeInserter());
96 PM.add(createX86PeepholeOptimizerPass());
98 if (PrintCode) // Print the register-allocated code
99 PM.add(createX86CodePrinterPass(std::cerr, *this));
101 PM.add(createX86CodePrinterPass(Out, *this));
103 // Delete machine code for this function
104 PM.add(createMachineCodeDeleter());
106 return false; // success!
109 /// addPassesToJITCompile - Add passes to the specified pass manager to
110 /// implement a fast dynamic compiler for this target. Return true if this is
111 /// not supported for this target.
113 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
114 // FIXME: Implement the switch instruction in the instruction selector!
115 PM.add(createLowerSwitchPass());
117 // FIXME: Implement the invoke/unwind instructions!
118 PM.add(createLowerInvokePass());
120 // FIXME: The code generator does not properly handle functions with
121 // unreachable basic blocks.
122 PM.add(createCFGSimplificationPass());
125 PM.add(createX86SimpleInstructionSelector(TM));
127 PM.add(createX86PatternInstructionSelector(TM));
129 // Run optional SSA-based machine code optimizations next...
131 PM.add(createX86SSAPeepholeOptimizerPass());
133 // FIXME: Add SSA based peephole optimizer here.
135 // Print the instruction selected machine code...
137 PM.add(createMachineFunctionPrinterPass());
139 // Perform register allocation to convert to a concrete x86 representation
140 PM.add(createRegisterAllocator());
143 PM.add(createMachineFunctionPrinterPass());
145 PM.add(createX86FloatingPointStackifierPass());
148 PM.add(createMachineFunctionPrinterPass());
150 // Insert prolog/epilog code. Eliminate abstract frame index references...
151 PM.add(createPrologEpilogCodeInserter());
153 PM.add(createX86PeepholeOptimizerPass());
155 if (PrintCode) // Print the register-allocated code
156 PM.add(createX86CodePrinterPass(std::cerr, TM));