1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeX86TTIPass(PassRegistry &);
35 class X86TTI : public ImmutablePass, public TargetTransformInfo {
36 const X86Subtarget *ST;
37 const X86TargetLowering *TLI;
39 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
40 /// are set if the result needs to be inserted and/or extracted from vectors.
41 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
44 X86TTI() : ImmutablePass(ID), ST(0), TLI(0) {
45 llvm_unreachable("This pass cannot be directly constructed");
48 X86TTI(const X86TargetMachine *TM)
49 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
50 TLI(TM->getTargetLowering()) {
51 initializeX86TTIPass(*PassRegistry::getPassRegistry());
54 virtual void initializePass() {
58 virtual void finalizePass() {
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
63 TargetTransformInfo::getAnalysisUsage(AU);
66 /// Pass identification.
69 /// Provide necessary pointer adjustments for the two base classes.
70 virtual void *getAdjustedAnalysisPointer(const void *ID) {
71 if (ID == &TargetTransformInfo::ID)
72 return (TargetTransformInfo*)this;
76 /// \name Scalar TTI Implementations
78 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
82 /// \name Vector TTI Implementations
85 virtual unsigned getNumberOfRegisters(bool Vector) const;
86 virtual unsigned getRegisterBitWidth(bool Vector) const;
87 virtual unsigned getMaximumUnrollFactor() const;
88 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
90 OperandValueKind) const;
91 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
92 int Index, Type *SubTp) const;
93 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
95 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
97 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
98 unsigned Index) const;
99 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
101 unsigned AddressSpace) const;
103 virtual unsigned getAddressComputationCost(Type *PtrTy, bool IsComplex) const;
105 virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
106 bool IsPairwiseForm) const;
111 } // end anonymous namespace
113 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
114 "X86 Target Transform Info", true, true, false)
118 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
119 return new X86TTI(TM);
123 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
129 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
130 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
131 // TODO: Currently the __builtin_popcount() implementation using SSE3
132 // instructions is inefficient. Once the problem is fixed, we should
133 // call ST->hasSSE3() instead of ST->hasPOPCNT().
134 return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
137 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
138 if (Vector && !ST->hasSSE1())
146 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
148 if (ST->hasAVX()) return 256;
149 if (ST->hasSSE1()) return 128;
159 unsigned X86TTI::getMaximumUnrollFactor() const {
163 // Sandybridge and Haswell have multiple execution ports and pipelined
171 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
172 OperandValueKind Op1Info,
173 OperandValueKind Op2Info) const {
174 // Legalize the type.
175 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
177 int ISD = TLI->InstructionOpcodeToISD(Opcode);
178 assert(ISD && "Invalid opcode");
180 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
181 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
182 // customize them to detect the cases where shift amount is a scalar one.
183 { ISD::SHL, MVT::v4i32, 1 },
184 { ISD::SRL, MVT::v4i32, 1 },
185 { ISD::SRA, MVT::v4i32, 1 },
186 { ISD::SHL, MVT::v8i32, 1 },
187 { ISD::SRL, MVT::v8i32, 1 },
188 { ISD::SRA, MVT::v8i32, 1 },
189 { ISD::SHL, MVT::v2i64, 1 },
190 { ISD::SRL, MVT::v2i64, 1 },
191 { ISD::SHL, MVT::v4i64, 1 },
192 { ISD::SRL, MVT::v4i64, 1 },
194 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
195 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
197 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
198 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
200 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
201 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
202 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
204 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
205 { ISD::SDIV, MVT::v32i8, 32*20 },
206 { ISD::SDIV, MVT::v16i16, 16*20 },
207 { ISD::SDIV, MVT::v8i32, 8*20 },
208 { ISD::SDIV, MVT::v4i64, 4*20 },
209 { ISD::UDIV, MVT::v32i8, 32*20 },
210 { ISD::UDIV, MVT::v16i16, 16*20 },
211 { ISD::UDIV, MVT::v8i32, 8*20 },
212 { ISD::UDIV, MVT::v4i64, 4*20 },
215 // Look for AVX2 lowering tricks.
217 int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second);
219 return LT.first * AVX2CostTable[Idx].Cost;
222 static const CostTblEntry<MVT::SimpleValueType>
223 SSE2UniformConstCostTable[] = {
224 // We don't correctly identify costs of casts because they are marked as
226 // Constant splats are cheaper for the following instructions.
227 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
228 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
229 { ISD::SHL, MVT::v4i32, 1 }, // pslld
230 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
232 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
233 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
234 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
235 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
237 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
238 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
239 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
242 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
244 int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second);
246 return LT.first * SSE2UniformConstCostTable[Idx].Cost;
250 static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = {
251 // We don't correctly identify costs of casts because they are marked as
253 // For some cases, where the shift amount is a scalar we would be able
254 // to generate better code. Unfortunately, when this is the case the value
255 // (the splat) will get hoisted out of the loop, thereby making it invisible
256 // to ISel. The cost model must return worst case assumptions because it is
257 // used for vectorization and we don't want to make vectorized code worse
259 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
260 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
261 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
262 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
264 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
265 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
266 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
267 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
269 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
270 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
271 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
272 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
274 // It is not a good idea to vectorize division. We have to scalarize it and
275 // in the process we will often end up having to spilling regular
276 // registers. The overhead of division is going to dominate most kernels
277 // anyways so try hard to prevent vectorization of division - it is
278 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
279 // to hide "20 cycles" for each lane.
280 { ISD::SDIV, MVT::v16i8, 16*20 },
281 { ISD::SDIV, MVT::v8i16, 8*20 },
282 { ISD::SDIV, MVT::v4i32, 4*20 },
283 { ISD::SDIV, MVT::v2i64, 2*20 },
284 { ISD::UDIV, MVT::v16i8, 16*20 },
285 { ISD::UDIV, MVT::v8i16, 8*20 },
286 { ISD::UDIV, MVT::v4i32, 4*20 },
287 { ISD::UDIV, MVT::v2i64, 2*20 },
291 int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second);
293 return LT.first * SSE2CostTable[Idx].Cost;
296 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = {
297 // We don't have to scalarize unsupported ops. We can issue two half-sized
298 // operations and we only need to extract the upper YMM half.
299 // Two ops + 1 extract + 1 insert = 4.
300 { ISD::MUL, MVT::v8i32, 4 },
301 { ISD::SUB, MVT::v8i32, 4 },
302 { ISD::ADD, MVT::v8i32, 4 },
303 { ISD::SUB, MVT::v4i64, 4 },
304 { ISD::ADD, MVT::v4i64, 4 },
305 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
306 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
307 // Because we believe v4i64 to be a legal type, we must also include the
308 // split factor of two in the cost table. Therefore, the cost here is 18
310 { ISD::MUL, MVT::v4i64, 18 },
313 // Look for AVX1 lowering tricks.
314 if (ST->hasAVX() && !ST->hasAVX2()) {
315 int Idx = CostTableLookup(AVX1CostTable, ISD, LT.second);
317 return LT.first * AVX1CostTable[Idx].Cost;
320 // Custom lowering of vectors.
321 static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = {
322 // A v2i64/v4i64 and multiply is custom lowered as a series of long
323 // multiplies(3), shifts(4) and adds(2).
324 { ISD::MUL, MVT::v2i64, 9 },
325 { ISD::MUL, MVT::v4i64, 9 },
327 int Idx = CostTableLookup(CustomLowered, ISD, LT.second);
329 return LT.first * CustomLowered[Idx].Cost;
331 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
332 // 2x pmuludq, 2x shuffle.
333 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
337 // Fallback to the default implementation.
338 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
342 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
344 // We only estimate the cost of reverse shuffles.
345 if (Kind != SK_Reverse)
346 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
348 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
350 if (LT.second.getSizeInBits() > 128)
351 Cost = 3; // Extract + insert + copy.
353 // Multiple by the number of parts.
354 return Cost * LT.first;
357 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
358 int ISD = TLI->InstructionOpcodeToISD(Opcode);
359 assert(ISD && "Invalid opcode");
361 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
362 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
364 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
366 // These are somewhat magic numbers justified by looking at the output of
367 // Intel's IACA, running some kernels and making sure when we take
368 // legalization into account the throughput will be overestimated.
369 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
370 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
371 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
373 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
374 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
375 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
377 // There are faster sequences for float conversions.
378 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
382 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
383 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
384 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
385 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
388 if (ST->hasSSE2() && !ST->hasAVX()) {
390 ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second);
392 return LTSrc.first * SSE2ConvTbl[Idx].Cost;
395 EVT SrcTy = TLI->getValueType(Src);
396 EVT DstTy = TLI->getValueType(Dst);
398 // The function getSimpleVT only handles simple value types.
399 if (!SrcTy.isSimple() || !DstTy.isSimple())
400 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
402 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
403 AVXConversionTbl[] = {
404 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
405 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
406 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
407 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
408 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
409 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
411 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
412 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
413 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
414 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
415 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
417 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
418 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
419 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
420 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
421 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
422 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
424 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
425 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
426 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
427 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
428 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
429 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
430 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
431 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
432 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
433 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
434 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
435 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
437 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
438 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
439 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
440 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
441 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
442 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
443 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
444 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
448 int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
449 SrcTy.getSimpleVT());
451 return AVXConversionTbl[Idx].Cost;
454 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
457 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
458 Type *CondTy) const {
459 // Legalize the type.
460 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
464 int ISD = TLI->InstructionOpcodeToISD(Opcode);
465 assert(ISD && "Invalid opcode");
467 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = {
468 { ISD::SETCC, MVT::v2f64, 1 },
469 { ISD::SETCC, MVT::v4f32, 1 },
470 { ISD::SETCC, MVT::v2i64, 1 },
471 { ISD::SETCC, MVT::v4i32, 1 },
472 { ISD::SETCC, MVT::v8i16, 1 },
473 { ISD::SETCC, MVT::v16i8, 1 },
476 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = {
477 { ISD::SETCC, MVT::v4f64, 1 },
478 { ISD::SETCC, MVT::v8f32, 1 },
479 // AVX1 does not support 8-wide integer compare.
480 { ISD::SETCC, MVT::v4i64, 4 },
481 { ISD::SETCC, MVT::v8i32, 4 },
482 { ISD::SETCC, MVT::v16i16, 4 },
483 { ISD::SETCC, MVT::v32i8, 4 },
486 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = {
487 { ISD::SETCC, MVT::v4i64, 1 },
488 { ISD::SETCC, MVT::v8i32, 1 },
489 { ISD::SETCC, MVT::v16i16, 1 },
490 { ISD::SETCC, MVT::v32i8, 1 },
494 int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy);
496 return LT.first * AVX2CostTbl[Idx].Cost;
500 int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy);
502 return LT.first * AVX1CostTbl[Idx].Cost;
505 if (ST->hasSSE42()) {
506 int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy);
508 return LT.first * SSE42CostTbl[Idx].Cost;
511 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
514 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
515 unsigned Index) const {
516 assert(Val->isVectorTy() && "This must be a vector type");
519 // Legalize the type.
520 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
522 // This type is legalized to a scalar type.
523 if (!LT.second.isVector())
526 // The type may be split. Normalize the index to the new type.
527 unsigned Width = LT.second.getVectorNumElements();
528 Index = Index % Width;
530 // Floating point scalars are already located in index #0.
531 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
535 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
538 unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
539 bool Extract) const {
540 assert (Ty->isVectorTy() && "Can only scalarize vectors");
543 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
545 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
547 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
553 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
554 unsigned AddressSpace) const {
555 // Handle non power of two vectors such as <3 x float>
556 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
557 unsigned NumElem = VTy->getVectorNumElements();
559 // Handle a few common cases:
561 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
562 // Cost = 64 bit store + extract + 32 bit store.
566 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
567 // Cost = 128 bit store + unpack + 64 bit store.
570 // Assume that all other non power-of-two numbers are scalarized.
571 if (!isPowerOf2_32(NumElem)) {
572 unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
573 VTy->getScalarType(),
576 unsigned SplitCost = getScalarizationOverhead(Src,
577 Opcode == Instruction::Load,
578 Opcode==Instruction::Store);
579 return NumElem * Cost + SplitCost;
583 // Legalize the type.
584 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
585 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
588 // Each load/store unit costs 1.
589 unsigned Cost = LT.first * 1;
591 // On Sandybridge 256bit load/stores are double pumped
592 // (but not on Haswell).
593 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
599 unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
600 // Address computations in vectorized code with non-consecutive addresses will
601 // likely result in more instructions compared to scalar code where the
602 // computation can more often be merged into the index mode. The resulting
603 // extra micro-ops can significantly decrease throughput.
604 unsigned NumVectorInstToHideOverhead = 10;
606 if (Ty->isVectorTy() && IsComplex)
607 return NumVectorInstToHideOverhead;
609 return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex);
612 unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy,
613 bool IsPairwise) const {
615 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
619 int ISD = TLI->InstructionOpcodeToISD(Opcode);
620 assert(ISD && "Invalid opcode");
622 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
623 // and make it as the cost.
625 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = {
626 { ISD::FADD, MVT::v2f64, 2 },
627 { ISD::FADD, MVT::v4f32, 4 },
628 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
629 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
630 { ISD::ADD, MVT::v8i16, 5 },
633 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = {
634 { ISD::FADD, MVT::v4f32, 4 },
635 { ISD::FADD, MVT::v4f64, 5 },
636 { ISD::FADD, MVT::v8f32, 7 },
637 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
638 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
639 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
640 { ISD::ADD, MVT::v8i16, 5 },
641 { ISD::ADD, MVT::v8i32, 5 },
644 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = {
645 { ISD::FADD, MVT::v2f64, 2 },
646 { ISD::FADD, MVT::v4f32, 4 },
647 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
648 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
649 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
652 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = {
653 { ISD::FADD, MVT::v4f32, 3 },
654 { ISD::FADD, MVT::v4f64, 3 },
655 { ISD::FADD, MVT::v8f32, 4 },
656 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
657 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
658 { ISD::ADD, MVT::v4i64, 3 },
659 { ISD::ADD, MVT::v8i16, 4 },
660 { ISD::ADD, MVT::v8i32, 5 },
665 int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy);
667 return LT.first * AVX1CostTblPairWise[Idx].Cost;
670 if (ST->hasSSE42()) {
671 int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy);
673 return LT.first * SSE42CostTblPairWise[Idx].Cost;
677 int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy);
679 return LT.first * AVX1CostTblNoPairWise[Idx].Cost;
682 if (ST->hasSSE42()) {
683 int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy);
685 return LT.first * SSE42CostTblNoPairWise[Idx].Cost;
689 return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise);