1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
18 #include "X86TargetMachine.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/IR/IntrinsicInst.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/CostTable.h"
23 #include "llvm/Target/TargetLowering.h"
26 #define DEBUG_TYPE "x86tti"
28 // Declare the pass initialization routine locally as target-specific passes
29 // don't have a target-wide initialization entry point, and so we rely on the
30 // pass constructor initialization.
32 void initializeX86TTIPass(PassRegistry &);
37 class X86TTI final : public ImmutablePass, public TargetTransformInfo {
38 const X86Subtarget *ST;
39 const X86TargetLowering *TLI;
41 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
42 /// are set if the result needs to be inserted and/or extracted from vectors.
43 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
46 X86TTI() : ImmutablePass(ID), ST(nullptr), TLI(nullptr) {
47 llvm_unreachable("This pass cannot be directly constructed");
50 X86TTI(const X86TargetMachine *TM)
51 : ImmutablePass(ID), ST(TM->getSubtargetImpl()),
52 TLI(TM->getSubtargetImpl()->getTargetLowering()) {
53 initializeX86TTIPass(*PassRegistry::getPassRegistry());
56 void initializePass() override {
60 void getAnalysisUsage(AnalysisUsage &AU) const override {
61 TargetTransformInfo::getAnalysisUsage(AU);
64 /// Pass identification.
67 /// Provide necessary pointer adjustments for the two base classes.
68 void *getAdjustedAnalysisPointer(const void *ID) override {
69 if (ID == &TargetTransformInfo::ID)
70 return (TargetTransformInfo*)this;
74 /// \name Scalar TTI Implementations
76 PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override;
80 /// \name Vector TTI Implementations
83 unsigned getNumberOfRegisters(bool Vector) const override;
84 unsigned getRegisterBitWidth(bool Vector) const override;
85 unsigned getMaximumUnrollFactor() const override;
86 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind,
87 OperandValueKind, OperandValueProperties,
88 OperandValueProperties) const override;
89 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
90 int Index, Type *SubTp) const override;
91 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
92 Type *Src) const override;
93 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
94 Type *CondTy) const override;
95 unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
96 unsigned Index) const override;
97 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
98 unsigned AddressSpace) const override;
100 unsigned getAddressComputationCost(Type *PtrTy,
101 bool IsComplex) const override;
103 unsigned getReductionCost(unsigned Opcode, Type *Ty,
104 bool IsPairwiseForm) const override;
106 unsigned getIntImmCost(int64_t) const;
108 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
110 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
111 Type *Ty) const override;
112 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
113 Type *Ty) const override;
118 } // end anonymous namespace
120 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
121 "X86 Target Transform Info", true, true, false)
125 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
126 return new X86TTI(TM);
130 //===----------------------------------------------------------------------===//
134 //===----------------------------------------------------------------------===//
136 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
137 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
138 // TODO: Currently the __builtin_popcount() implementation using SSE3
139 // instructions is inefficient. Once the problem is fixed, we should
140 // call ST->hasSSE3() instead of ST->hasPOPCNT().
141 return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
144 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
145 if (Vector && !ST->hasSSE1())
149 if (Vector && ST->hasAVX512())
156 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
158 if (ST->hasAVX512()) return 512;
159 if (ST->hasAVX()) return 256;
160 if (ST->hasSSE1()) return 128;
170 unsigned X86TTI::getMaximumUnrollFactor() const {
174 // Sandybridge and Haswell have multiple execution ports and pipelined
182 unsigned X86TTI::getArithmeticInstrCost(
183 unsigned Opcode, Type *Ty, OperandValueKind Op1Info,
184 OperandValueKind Op2Info, OperandValueProperties Opd1PropInfo,
185 OperandValueProperties Opd2PropInfo) const {
186 // Legalize the type.
187 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
189 int ISD = TLI->InstructionOpcodeToISD(Opcode);
190 assert(ISD && "Invalid opcode");
192 if (ISD == ISD::SDIV &&
193 Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
194 Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
195 // On X86, vector signed division by constants power-of-two are
196 // normally expanded to the sequence SRA + SRL + ADD + SRA.
197 // The OperandValue properties many not be same as that of previous
198 // operation;conservatively assume OP_None.
200 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info,
201 TargetTransformInfo::OP_None,
202 TargetTransformInfo::OP_None);
203 Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info,
204 TargetTransformInfo::OP_None,
205 TargetTransformInfo::OP_None);
206 Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info,
207 TargetTransformInfo::OP_None,
208 TargetTransformInfo::OP_None);
213 static const CostTblEntry<MVT::SimpleValueType>
214 AVX2UniformConstCostTable[] = {
215 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
216 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
217 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
218 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
221 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
223 int Idx = CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second);
225 return LT.first * AVX2UniformConstCostTable[Idx].Cost;
228 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTable[] = {
229 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
230 // customize them to detect the cases where shift amount is a scalar one.
231 { ISD::SHL, MVT::v4i32, 1 },
232 { ISD::SRL, MVT::v4i32, 1 },
233 { ISD::SRA, MVT::v4i32, 1 },
234 { ISD::SHL, MVT::v8i32, 1 },
235 { ISD::SRL, MVT::v8i32, 1 },
236 { ISD::SRA, MVT::v8i32, 1 },
237 { ISD::SHL, MVT::v2i64, 1 },
238 { ISD::SRL, MVT::v2i64, 1 },
239 { ISD::SHL, MVT::v4i64, 1 },
240 { ISD::SRL, MVT::v4i64, 1 },
242 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
243 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
245 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
246 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
248 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
249 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
250 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
252 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
253 { ISD::SDIV, MVT::v32i8, 32*20 },
254 { ISD::SDIV, MVT::v16i16, 16*20 },
255 { ISD::SDIV, MVT::v8i32, 8*20 },
256 { ISD::SDIV, MVT::v4i64, 4*20 },
257 { ISD::UDIV, MVT::v32i8, 32*20 },
258 { ISD::UDIV, MVT::v16i16, 16*20 },
259 { ISD::UDIV, MVT::v8i32, 8*20 },
260 { ISD::UDIV, MVT::v4i64, 4*20 },
263 // Look for AVX2 lowering tricks.
265 if (ISD == ISD::SHL && LT.second == MVT::v16i16 &&
266 (Op2Info == TargetTransformInfo::OK_UniformConstantValue ||
267 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue))
268 // On AVX2, a packed v16i16 shift left by a constant build_vector
269 // is lowered into a vector multiply (vpmullw).
272 int Idx = CostTableLookup(AVX2CostTable, ISD, LT.second);
274 return LT.first * AVX2CostTable[Idx].Cost;
277 static const CostTblEntry<MVT::SimpleValueType>
278 SSE2UniformConstCostTable[] = {
279 // We don't correctly identify costs of casts because they are marked as
281 // Constant splats are cheaper for the following instructions.
282 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
283 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
284 { ISD::SHL, MVT::v4i32, 1 }, // pslld
285 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
287 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
288 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
289 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
290 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
292 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
293 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
294 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
296 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
297 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
298 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
299 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
302 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
305 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
306 return LT.first * 15;
308 int Idx = CostTableLookup(SSE2UniformConstCostTable, ISD, LT.second);
310 return LT.first * SSE2UniformConstCostTable[Idx].Cost;
313 if (ISD == ISD::SHL &&
314 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) {
316 if ((VT == MVT::v8i16 && ST->hasSSE2()) ||
317 (VT == MVT::v4i32 && ST->hasSSE41()))
318 // Vector shift left by non uniform constant can be lowered
319 // into vector multiply (pmullw/pmulld).
321 if (VT == MVT::v4i32 && ST->hasSSE2())
322 // A vector shift left by non uniform constant is converted
323 // into a vector multiply; the new multiply is eventually
324 // lowered into a sequence of shuffles and 2 x pmuludq.
328 static const CostTblEntry<MVT::SimpleValueType> SSE2CostTable[] = {
329 // We don't correctly identify costs of casts because they are marked as
331 // For some cases, where the shift amount is a scalar we would be able
332 // to generate better code. Unfortunately, when this is the case the value
333 // (the splat) will get hoisted out of the loop, thereby making it invisible
334 // to ISel. The cost model must return worst case assumptions because it is
335 // used for vectorization and we don't want to make vectorized code worse
337 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
338 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
339 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
340 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
341 { ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized.
343 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
344 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
345 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
346 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
348 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
349 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
350 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
351 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
353 // It is not a good idea to vectorize division. We have to scalarize it and
354 // in the process we will often end up having to spilling regular
355 // registers. The overhead of division is going to dominate most kernels
356 // anyways so try hard to prevent vectorization of division - it is
357 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
358 // to hide "20 cycles" for each lane.
359 { ISD::SDIV, MVT::v16i8, 16*20 },
360 { ISD::SDIV, MVT::v8i16, 8*20 },
361 { ISD::SDIV, MVT::v4i32, 4*20 },
362 { ISD::SDIV, MVT::v2i64, 2*20 },
363 { ISD::UDIV, MVT::v16i8, 16*20 },
364 { ISD::UDIV, MVT::v8i16, 8*20 },
365 { ISD::UDIV, MVT::v4i32, 4*20 },
366 { ISD::UDIV, MVT::v2i64, 2*20 },
370 int Idx = CostTableLookup(SSE2CostTable, ISD, LT.second);
372 return LT.first * SSE2CostTable[Idx].Cost;
375 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTable[] = {
376 // We don't have to scalarize unsupported ops. We can issue two half-sized
377 // operations and we only need to extract the upper YMM half.
378 // Two ops + 1 extract + 1 insert = 4.
379 { ISD::MUL, MVT::v16i16, 4 },
380 { ISD::MUL, MVT::v8i32, 4 },
381 { ISD::SUB, MVT::v8i32, 4 },
382 { ISD::ADD, MVT::v8i32, 4 },
383 { ISD::SUB, MVT::v4i64, 4 },
384 { ISD::ADD, MVT::v4i64, 4 },
385 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
386 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
387 // Because we believe v4i64 to be a legal type, we must also include the
388 // split factor of two in the cost table. Therefore, the cost here is 18
390 { ISD::MUL, MVT::v4i64, 18 },
393 // Look for AVX1 lowering tricks.
394 if (ST->hasAVX() && !ST->hasAVX2()) {
397 // v16i16 and v8i32 shifts by non-uniform constants are lowered into a
398 // sequence of extract + two vector multiply + insert.
399 if (ISD == ISD::SHL && (VT == MVT::v8i32 || VT == MVT::v16i16) &&
400 Op2Info == TargetTransformInfo::OK_NonUniformConstantValue)
403 int Idx = CostTableLookup(AVX1CostTable, ISD, VT);
405 return LT.first * AVX1CostTable[Idx].Cost;
408 // Custom lowering of vectors.
409 static const CostTblEntry<MVT::SimpleValueType> CustomLowered[] = {
410 // A v2i64/v4i64 and multiply is custom lowered as a series of long
411 // multiplies(3), shifts(4) and adds(2).
412 { ISD::MUL, MVT::v2i64, 9 },
413 { ISD::MUL, MVT::v4i64, 9 },
415 int Idx = CostTableLookup(CustomLowered, ISD, LT.second);
417 return LT.first * CustomLowered[Idx].Cost;
419 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
420 // 2x pmuludq, 2x shuffle.
421 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
425 // Fallback to the default implementation.
426 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
430 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
432 // We only estimate the cost of reverse and alternate shuffles.
433 if (Kind != SK_Reverse && Kind != SK_Alternate)
434 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
436 if (Kind == SK_Reverse) {
437 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
439 if (LT.second.getSizeInBits() > 128)
440 Cost = 3; // Extract + insert + copy.
442 // Multiple by the number of parts.
443 return Cost * LT.first;
446 if (Kind == SK_Alternate) {
447 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
448 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
449 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
451 // The backend knows how to generate a single VEX.256 version of
452 // instruction VPBLENDW if the target supports AVX2.
453 if (ST->hasAVX2() && LT.second == MVT::v16i16)
456 static const CostTblEntry<MVT::SimpleValueType> AVXAltShuffleTbl[] = {
457 {ISD::VECTOR_SHUFFLE, MVT::v4i64, 1}, // vblendpd
458 {ISD::VECTOR_SHUFFLE, MVT::v4f64, 1}, // vblendpd
460 {ISD::VECTOR_SHUFFLE, MVT::v8i32, 1}, // vblendps
461 {ISD::VECTOR_SHUFFLE, MVT::v8f32, 1}, // vblendps
463 // This shuffle is custom lowered into a sequence of:
464 // 2x vextractf128 , 2x vpblendw , 1x vinsertf128
465 {ISD::VECTOR_SHUFFLE, MVT::v16i16, 5},
467 // This shuffle is custom lowered into a long sequence of:
468 // 2x vextractf128 , 4x vpshufb , 2x vpor , 1x vinsertf128
469 {ISD::VECTOR_SHUFFLE, MVT::v32i8, 9}
473 int Idx = CostTableLookup(AVXAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
475 return LT.first * AVXAltShuffleTbl[Idx].Cost;
478 static const CostTblEntry<MVT::SimpleValueType> SSE41AltShuffleTbl[] = {
479 // These are lowered into movsd.
480 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
481 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1},
483 // packed float vectors with four elements are lowered into BLENDI dag
484 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'.
485 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1},
486 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
488 // This shuffle generates a single pshufw.
489 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1},
491 // There is no instruction that matches a v16i8 alternate shuffle.
492 // The backend will expand it into the sequence 'pshufb + pshufb + or'.
493 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3}
496 if (ST->hasSSE41()) {
497 int Idx = CostTableLookup(SSE41AltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
499 return LT.first * SSE41AltShuffleTbl[Idx].Cost;
502 static const CostTblEntry<MVT::SimpleValueType> SSSE3AltShuffleTbl[] = {
503 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd
504 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd
506 // SSE3 doesn't have 'blendps'. The following shuffles are expanded into
507 // the sequence 'shufps + pshufd'
508 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
509 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
511 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 3}, // pshufb + pshufb + or
512 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 3} // pshufb + pshufb + or
515 if (ST->hasSSSE3()) {
516 int Idx = CostTableLookup(SSSE3AltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
518 return LT.first * SSSE3AltShuffleTbl[Idx].Cost;
521 static const CostTblEntry<MVT::SimpleValueType> SSEAltShuffleTbl[] = {
522 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, // movsd
523 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, // movsd
525 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}, // shufps + pshufd
526 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd
528 // This is expanded into a long sequence of four extract + four insert.
529 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 8}, // 4 x pextrw + 4 pinsrw.
531 // 8 x (pinsrw + pextrw + and + movb + movzb + or)
532 {ISD::VECTOR_SHUFFLE, MVT::v16i8, 48}
535 // Fall-back (SSE3 and SSE2).
536 int Idx = CostTableLookup(SSEAltShuffleTbl, ISD::VECTOR_SHUFFLE, LT.second);
538 return LT.first * SSEAltShuffleTbl[Idx].Cost;
539 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
542 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
545 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
546 int ISD = TLI->InstructionOpcodeToISD(Opcode);
547 assert(ISD && "Invalid opcode");
549 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
550 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
552 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
554 // These are somewhat magic numbers justified by looking at the output of
555 // Intel's IACA, running some kernels and making sure when we take
556 // legalization into account the throughput will be overestimated.
557 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
558 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
559 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
560 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
561 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
562 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
563 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
564 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
565 // There are faster sequences for float conversions.
566 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
567 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
568 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
569 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
570 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
571 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
572 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
573 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
576 if (ST->hasSSE2() && !ST->hasAVX()) {
578 ConvertCostTableLookup(SSE2ConvTbl, ISD, LTDest.second, LTSrc.second);
580 return LTSrc.first * SSE2ConvTbl[Idx].Cost;
583 EVT SrcTy = TLI->getValueType(Src);
584 EVT DstTy = TLI->getValueType(Dst);
586 // The function getSimpleVT only handles simple value types.
587 if (!SrcTy.isSimple() || !DstTy.isSimple())
588 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
590 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
591 AVX2ConversionTbl[] = {
592 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
593 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
594 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
595 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
596 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
597 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
598 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
599 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
600 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
601 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
602 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
603 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 3 },
604 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
605 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
606 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
607 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
609 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
610 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 },
611 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 2 },
612 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2 },
613 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 2 },
614 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 4 },
617 static const TypeConversionCostTblEntry<MVT::SimpleValueType>
618 AVXConversionTbl[] = {
619 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
620 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
621 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 7 },
622 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
623 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 7 },
624 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
625 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
626 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
627 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 6 },
628 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
629 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
630 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
631 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
632 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
633 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
634 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
636 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
637 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 },
638 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 4 },
639 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 4 },
640 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 5 },
641 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 4 },
642 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 9 },
644 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
645 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
646 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
647 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
648 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
649 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
650 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
651 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
652 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
653 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
654 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
655 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
657 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
658 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
659 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
660 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
661 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
662 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
663 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
664 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
665 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
666 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
667 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
668 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
669 // The generic code to compute the scalar overhead is currently broken.
670 // Workaround this limitation by estimating the scalarization overhead
671 // here. We have roughly 10 instructions per scalar element.
672 // Multiply that by the vector width.
673 // FIXME: remove that when PR19268 is fixed.
674 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
675 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i64, 4*10 },
677 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
678 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
679 // This node is expanded into scalarized operations but BasicTTI is overly
680 // optimistic estimating its cost. It computes 3 per element (one
681 // vector-extract, one scalar conversion and one vector-insert). The
682 // problem is that the inserts form a read-modify-write chain so latency
683 // should be factored in too. Inflating the cost per element by 1.
684 { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f32, 8*4 },
685 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f64, 4*4 },
689 int Idx = ConvertCostTableLookup(AVX2ConversionTbl, ISD,
690 DstTy.getSimpleVT(), SrcTy.getSimpleVT());
692 return AVX2ConversionTbl[Idx].Cost;
696 int Idx = ConvertCostTableLookup(AVXConversionTbl, ISD, DstTy.getSimpleVT(),
697 SrcTy.getSimpleVT());
699 return AVXConversionTbl[Idx].Cost;
702 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
705 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
706 Type *CondTy) const {
707 // Legalize the type.
708 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
712 int ISD = TLI->InstructionOpcodeToISD(Opcode);
713 assert(ISD && "Invalid opcode");
715 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTbl[] = {
716 { ISD::SETCC, MVT::v2f64, 1 },
717 { ISD::SETCC, MVT::v4f32, 1 },
718 { ISD::SETCC, MVT::v2i64, 1 },
719 { ISD::SETCC, MVT::v4i32, 1 },
720 { ISD::SETCC, MVT::v8i16, 1 },
721 { ISD::SETCC, MVT::v16i8, 1 },
724 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTbl[] = {
725 { ISD::SETCC, MVT::v4f64, 1 },
726 { ISD::SETCC, MVT::v8f32, 1 },
727 // AVX1 does not support 8-wide integer compare.
728 { ISD::SETCC, MVT::v4i64, 4 },
729 { ISD::SETCC, MVT::v8i32, 4 },
730 { ISD::SETCC, MVT::v16i16, 4 },
731 { ISD::SETCC, MVT::v32i8, 4 },
734 static const CostTblEntry<MVT::SimpleValueType> AVX2CostTbl[] = {
735 { ISD::SETCC, MVT::v4i64, 1 },
736 { ISD::SETCC, MVT::v8i32, 1 },
737 { ISD::SETCC, MVT::v16i16, 1 },
738 { ISD::SETCC, MVT::v32i8, 1 },
742 int Idx = CostTableLookup(AVX2CostTbl, ISD, MTy);
744 return LT.first * AVX2CostTbl[Idx].Cost;
748 int Idx = CostTableLookup(AVX1CostTbl, ISD, MTy);
750 return LT.first * AVX1CostTbl[Idx].Cost;
753 if (ST->hasSSE42()) {
754 int Idx = CostTableLookup(SSE42CostTbl, ISD, MTy);
756 return LT.first * SSE42CostTbl[Idx].Cost;
759 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
762 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
763 unsigned Index) const {
764 assert(Val->isVectorTy() && "This must be a vector type");
767 // Legalize the type.
768 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
770 // This type is legalized to a scalar type.
771 if (!LT.second.isVector())
774 // The type may be split. Normalize the index to the new type.
775 unsigned Width = LT.second.getVectorNumElements();
776 Index = Index % Width;
778 // Floating point scalars are already located in index #0.
779 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
783 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
786 unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert,
787 bool Extract) const {
788 assert (Ty->isVectorTy() && "Can only scalarize vectors");
791 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
793 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
795 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
801 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
802 unsigned AddressSpace) const {
803 // Handle non-power-of-two vectors such as <3 x float>
804 if (VectorType *VTy = dyn_cast<VectorType>(Src)) {
805 unsigned NumElem = VTy->getVectorNumElements();
807 // Handle a few common cases:
809 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32)
810 // Cost = 64 bit store + extract + 32 bit store.
814 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64)
815 // Cost = 128 bit store + unpack + 64 bit store.
818 // Assume that all other non-power-of-two numbers are scalarized.
819 if (!isPowerOf2_32(NumElem)) {
820 unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode,
821 VTy->getScalarType(),
824 unsigned SplitCost = getScalarizationOverhead(Src,
825 Opcode == Instruction::Load,
826 Opcode==Instruction::Store);
827 return NumElem * Cost + SplitCost;
831 // Legalize the type.
832 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
833 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
836 // Each load/store unit costs 1.
837 unsigned Cost = LT.first * 1;
839 // On Sandybridge 256bit load/stores are double pumped
840 // (but not on Haswell).
841 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
847 unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const {
848 // Address computations in vectorized code with non-consecutive addresses will
849 // likely result in more instructions compared to scalar code where the
850 // computation can more often be merged into the index mode. The resulting
851 // extra micro-ops can significantly decrease throughput.
852 unsigned NumVectorInstToHideOverhead = 10;
854 if (Ty->isVectorTy() && IsComplex)
855 return NumVectorInstToHideOverhead;
857 return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex);
860 unsigned X86TTI::getReductionCost(unsigned Opcode, Type *ValTy,
861 bool IsPairwise) const {
863 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
867 int ISD = TLI->InstructionOpcodeToISD(Opcode);
868 assert(ISD && "Invalid opcode");
870 // We use the Intel Architecture Code Analyzer(IACA) to measure the throughput
871 // and make it as the cost.
873 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblPairWise[] = {
874 { ISD::FADD, MVT::v2f64, 2 },
875 { ISD::FADD, MVT::v4f32, 4 },
876 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
877 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
878 { ISD::ADD, MVT::v8i16, 5 },
881 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblPairWise[] = {
882 { ISD::FADD, MVT::v4f32, 4 },
883 { ISD::FADD, MVT::v4f64, 5 },
884 { ISD::FADD, MVT::v8f32, 7 },
885 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
886 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.5".
887 { ISD::ADD, MVT::v4i64, 5 }, // The data reported by the IACA tool is "4.8".
888 { ISD::ADD, MVT::v8i16, 5 },
889 { ISD::ADD, MVT::v8i32, 5 },
892 static const CostTblEntry<MVT::SimpleValueType> SSE42CostTblNoPairWise[] = {
893 { ISD::FADD, MVT::v2f64, 2 },
894 { ISD::FADD, MVT::v4f32, 4 },
895 { ISD::ADD, MVT::v2i64, 2 }, // The data reported by the IACA tool is "1.6".
896 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "3.3".
897 { ISD::ADD, MVT::v8i16, 4 }, // The data reported by the IACA tool is "4.3".
900 static const CostTblEntry<MVT::SimpleValueType> AVX1CostTblNoPairWise[] = {
901 { ISD::FADD, MVT::v4f32, 3 },
902 { ISD::FADD, MVT::v4f64, 3 },
903 { ISD::FADD, MVT::v8f32, 4 },
904 { ISD::ADD, MVT::v2i64, 1 }, // The data reported by the IACA tool is "1.5".
905 { ISD::ADD, MVT::v4i32, 3 }, // The data reported by the IACA tool is "2.8".
906 { ISD::ADD, MVT::v4i64, 3 },
907 { ISD::ADD, MVT::v8i16, 4 },
908 { ISD::ADD, MVT::v8i32, 5 },
913 int Idx = CostTableLookup(AVX1CostTblPairWise, ISD, MTy);
915 return LT.first * AVX1CostTblPairWise[Idx].Cost;
918 if (ST->hasSSE42()) {
919 int Idx = CostTableLookup(SSE42CostTblPairWise, ISD, MTy);
921 return LT.first * SSE42CostTblPairWise[Idx].Cost;
925 int Idx = CostTableLookup(AVX1CostTblNoPairWise, ISD, MTy);
927 return LT.first * AVX1CostTblNoPairWise[Idx].Cost;
930 if (ST->hasSSE42()) {
931 int Idx = CostTableLookup(SSE42CostTblNoPairWise, ISD, MTy);
933 return LT.first * SSE42CostTblNoPairWise[Idx].Cost;
937 return TargetTransformInfo::getReductionCost(Opcode, ValTy, IsPairwise);
940 /// \brief Calculate the cost of materializing a 64-bit value. This helper
941 /// method might only calculate a fraction of a larger immediate. Therefore it
942 /// is valid to return a cost of ZERO.
943 unsigned X86TTI::getIntImmCost(int64_t Val) const {
950 return 2 * TCC_Basic;
953 unsigned X86TTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
954 assert(Ty->isIntegerTy());
956 unsigned BitSize = Ty->getPrimitiveSizeInBits();
960 // Never hoist constants larger than 128bit, because this might lead to
961 // incorrect code generation or assertions in codegen.
962 // Fixme: Create a cost model for types larger than i128 once the codegen
963 // issues have been fixed.
970 // Sign-extend all constants to a multiple of 64-bit.
973 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
975 // Split the constant into 64-bit chunks and calculate the cost for each
978 for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
979 APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
980 int64_t Val = Tmp.getSExtValue();
981 Cost += getIntImmCost(Val);
983 // We need at least one instruction to materialze the constant.
984 return std::max(1U, Cost);
987 unsigned X86TTI::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
989 assert(Ty->isIntegerTy());
991 unsigned BitSize = Ty->getPrimitiveSizeInBits();
992 // There is no cost model for constants with a bit size of 0. Return TCC_Free
993 // here, so that constant hoisting will ignore this constant.
997 unsigned ImmIdx = ~0U;
999 default: return TCC_Free;
1000 case Instruction::GetElementPtr:
1001 // Always hoist the base address of a GetElementPtr. This prevents the
1002 // creation of new constants for every base constant that gets constant
1003 // folded with the offset.
1005 return 2 * TCC_Basic;
1007 case Instruction::Store:
1010 case Instruction::Add:
1011 case Instruction::Sub:
1012 case Instruction::Mul:
1013 case Instruction::UDiv:
1014 case Instruction::SDiv:
1015 case Instruction::URem:
1016 case Instruction::SRem:
1017 case Instruction::And:
1018 case Instruction::Or:
1019 case Instruction::Xor:
1020 case Instruction::ICmp:
1023 // Always return TCC_Free for the shift value of a shift instruction.
1024 case Instruction::Shl:
1025 case Instruction::LShr:
1026 case Instruction::AShr:
1030 case Instruction::Trunc:
1031 case Instruction::ZExt:
1032 case Instruction::SExt:
1033 case Instruction::IntToPtr:
1034 case Instruction::PtrToInt:
1035 case Instruction::BitCast:
1036 case Instruction::PHI:
1037 case Instruction::Call:
1038 case Instruction::Select:
1039 case Instruction::Ret:
1040 case Instruction::Load:
1044 if (Idx == ImmIdx) {
1045 unsigned NumConstants = (BitSize + 63) / 64;
1046 unsigned Cost = X86TTI::getIntImmCost(Imm, Ty);
1047 return (Cost <= NumConstants * TCC_Basic)
1048 ? static_cast<unsigned>(TCC_Free)
1052 return X86TTI::getIntImmCost(Imm, Ty);
1055 unsigned X86TTI::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
1056 const APInt &Imm, Type *Ty) const {
1057 assert(Ty->isIntegerTy());
1059 unsigned BitSize = Ty->getPrimitiveSizeInBits();
1060 // There is no cost model for constants with a bit size of 0. Return TCC_Free
1061 // here, so that constant hoisting will ignore this constant.
1066 default: return TCC_Free;
1067 case Intrinsic::sadd_with_overflow:
1068 case Intrinsic::uadd_with_overflow:
1069 case Intrinsic::ssub_with_overflow:
1070 case Intrinsic::usub_with_overflow:
1071 case Intrinsic::smul_with_overflow:
1072 case Intrinsic::umul_with_overflow:
1073 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
1076 case Intrinsic::experimental_stackmap:
1077 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
1080 case Intrinsic::experimental_patchpoint_void:
1081 case Intrinsic::experimental_patchpoint_i64:
1082 if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
1086 return X86TTI::getIntImmCost(Imm, Ty);