1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeX86TTIPass(PassRegistry &);
35 class X86TTI : public ImmutablePass, public TargetTransformInfo {
36 const X86TargetMachine *TM;
37 const X86Subtarget *ST;
38 const X86TargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 X86TTI(const X86TargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeX86TTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
79 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
83 /// \name Vector TTI Implementations
86 virtual unsigned getNumberOfRegisters(bool Vector) const;
87 virtual unsigned getRegisterBitWidth(bool Vector) const;
88 virtual unsigned getMaximumUnrollFactor() const;
89 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
91 OperandValueKind) const;
92 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
93 int Index, Type *SubTp) const;
94 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
96 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
98 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
99 unsigned Index) const;
100 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
102 unsigned AddressSpace) const;
107 } // end anonymous namespace
109 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
110 "X86 Target Transform Info", true, true, false)
114 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
115 return new X86TTI(TM);
119 //===----------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
125 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
126 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
127 // TODO: Currently the __builtin_popcount() implementation using SSE3
128 // instructions is inefficient. Once the problem is fixed, we should
129 // call ST->hasSSE3() instead of ST->hasSSE4().
130 return ST->hasSSE41() ? PSK_FastHardware : PSK_Software;
133 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
134 if (Vector && !ST->hasSSE1())
142 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
144 if (ST->hasAVX()) return 256;
145 if (ST->hasSSE1()) return 128;
155 unsigned X86TTI::getMaximumUnrollFactor() const {
159 // Sandybridge and Haswell have multiple execution ports and pipelined
167 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
168 OperandValueKind Op1Info,
169 OperandValueKind Op2Info) const {
170 // Legalize the type.
171 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
173 int ISD = TLI->InstructionOpcodeToISD(Opcode);
174 assert(ISD && "Invalid opcode");
176 static const CostTblEntry<MVT> AVX2CostTable[] = {
177 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
178 // customize them to detect the cases where shift amount is a scalar one.
179 { ISD::SHL, MVT::v4i32, 1 },
180 { ISD::SRL, MVT::v4i32, 1 },
181 { ISD::SRA, MVT::v4i32, 1 },
182 { ISD::SHL, MVT::v8i32, 1 },
183 { ISD::SRL, MVT::v8i32, 1 },
184 { ISD::SRA, MVT::v8i32, 1 },
185 { ISD::SHL, MVT::v2i64, 1 },
186 { ISD::SRL, MVT::v2i64, 1 },
187 { ISD::SHL, MVT::v4i64, 1 },
188 { ISD::SRL, MVT::v4i64, 1 },
190 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
191 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
193 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
194 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
196 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
197 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
198 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
201 // Look for AVX2 lowering tricks.
203 int Idx = CostTableLookup<MVT>(AVX2CostTable, array_lengthof(AVX2CostTable),
206 return LT.first * AVX2CostTable[Idx].Cost;
209 static const CostTblEntry<MVT> SSE2UniformConstCostTable[] = {
210 // We don't correctly identify costs of casts because they are marked as
212 // Constant splats are cheaper for the following instructions.
213 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
214 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
215 { ISD::SHL, MVT::v4i32, 1 }, // pslld
216 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
218 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
219 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
220 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
221 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
223 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
224 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
225 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
228 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
230 int Idx = CostTableLookup<MVT>(SSE2UniformConstCostTable,
231 array_lengthof(SSE2UniformConstCostTable),
234 return LT.first * SSE2UniformConstCostTable[Idx].Cost;
238 static const CostTblEntry<MVT> SSE2CostTable[] = {
239 // We don't correctly identify costs of casts because they are marked as
241 // For some cases, where the shift amount is a scalar we would be able
242 // to generate better code. Unfortunately, when this is the case the value
243 // (the splat) will get hoisted out of the loop, thereby making it invisible
244 // to ISel. The cost model must return worst case assumptions because it is
245 // used for vectorization and we don't want to make vectorized code worse
247 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
248 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
249 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
250 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
252 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
253 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
254 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
255 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
257 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
258 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
259 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
260 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
264 int Idx = CostTableLookup<MVT>(SSE2CostTable, array_lengthof(SSE2CostTable),
267 return LT.first * SSE2CostTable[Idx].Cost;
270 static const CostTblEntry<MVT> AVX1CostTable[] = {
271 // We don't have to scalarize unsupported ops. We can issue two half-sized
272 // operations and we only need to extract the upper YMM half.
273 // Two ops + 1 extract + 1 insert = 4.
274 { ISD::MUL, MVT::v8i32, 4 },
275 { ISD::SUB, MVT::v8i32, 4 },
276 { ISD::ADD, MVT::v8i32, 4 },
277 { ISD::SUB, MVT::v4i64, 4 },
278 { ISD::ADD, MVT::v4i64, 4 },
279 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
280 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
281 // Because we believe v4i64 to be a legal type, we must also include the
282 // split factor of two in the cost table. Therefore, the cost here is 18
284 { ISD::MUL, MVT::v4i64, 18 },
287 // Look for AVX1 lowering tricks.
288 if (ST->hasAVX() && !ST->hasAVX2()) {
289 int Idx = CostTableLookup<MVT>(AVX1CostTable, array_lengthof(AVX1CostTable),
292 return LT.first * AVX1CostTable[Idx].Cost;
295 // Custom lowering of vectors.
296 static const CostTblEntry<MVT> CustomLowered[] = {
297 // A v2i64/v4i64 and multiply is custom lowered as a series of long
298 // multiplies(3), shifts(4) and adds(2).
299 { ISD::MUL, MVT::v2i64, 9 },
300 { ISD::MUL, MVT::v4i64, 9 },
302 int Idx = CostTableLookup<MVT>(CustomLowered, array_lengthof(CustomLowered),
305 return LT.first * CustomLowered[Idx].Cost;
307 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
308 // 2x pmuludq, 2x shuffle.
309 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
313 // Fallback to the default implementation.
314 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
318 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
320 // We only estimate the cost of reverse shuffles.
321 if (Kind != SK_Reverse)
322 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
324 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
326 if (LT.second.getSizeInBits() > 128)
327 Cost = 3; // Extract + insert + copy.
329 // Multiple by the number of parts.
330 return Cost * LT.first;
333 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
334 int ISD = TLI->InstructionOpcodeToISD(Opcode);
335 assert(ISD && "Invalid opcode");
337 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
338 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
340 static const TypeConversionCostTblEntry<MVT> SSE2ConvTbl[] = {
341 // These are somewhat magic numbers justified by looking at the output of
342 // Intel's IACA, running some kernels and making sure when we take
343 // legalization into account the throughput will be overestimated.
344 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
345 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
346 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
347 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
348 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
349 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
350 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
351 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
352 // There are faster sequences for float conversions.
353 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
354 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
355 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
356 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
357 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
358 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
359 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
360 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
363 if (ST->hasSSE2() && !ST->hasAVX()) {
364 int Idx = ConvertCostTableLookup<MVT>(SSE2ConvTbl,
365 array_lengthof(SSE2ConvTbl),
366 ISD, LTDest.second, LTSrc.second);
368 return LTSrc.first * SSE2ConvTbl[Idx].Cost;
371 EVT SrcTy = TLI->getValueType(Src);
372 EVT DstTy = TLI->getValueType(Dst);
374 // The function getSimpleVT only handles simple value types.
375 if (!SrcTy.isSimple() || !DstTy.isSimple())
376 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
378 static const TypeConversionCostTblEntry<MVT> AVXConversionTbl[] = {
379 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
380 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
381 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
382 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
383 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
384 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
386 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
387 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
388 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
389 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
390 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
391 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
392 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
393 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
394 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
395 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
396 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
397 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
399 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
400 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
401 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
402 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
403 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
404 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
405 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
406 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
407 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
408 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
409 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
410 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
412 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
413 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
414 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
415 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
416 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
417 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
418 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
419 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
423 int Idx = ConvertCostTableLookup<MVT>(AVXConversionTbl,
424 array_lengthof(AVXConversionTbl),
425 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
427 return AVXConversionTbl[Idx].Cost;
430 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
433 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
434 Type *CondTy) const {
435 // Legalize the type.
436 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
440 int ISD = TLI->InstructionOpcodeToISD(Opcode);
441 assert(ISD && "Invalid opcode");
443 static const CostTblEntry<MVT> SSE42CostTbl[] = {
444 { ISD::SETCC, MVT::v2f64, 1 },
445 { ISD::SETCC, MVT::v4f32, 1 },
446 { ISD::SETCC, MVT::v2i64, 1 },
447 { ISD::SETCC, MVT::v4i32, 1 },
448 { ISD::SETCC, MVT::v8i16, 1 },
449 { ISD::SETCC, MVT::v16i8, 1 },
452 static const CostTblEntry<MVT> AVX1CostTbl[] = {
453 { ISD::SETCC, MVT::v4f64, 1 },
454 { ISD::SETCC, MVT::v8f32, 1 },
455 // AVX1 does not support 8-wide integer compare.
456 { ISD::SETCC, MVT::v4i64, 4 },
457 { ISD::SETCC, MVT::v8i32, 4 },
458 { ISD::SETCC, MVT::v16i16, 4 },
459 { ISD::SETCC, MVT::v32i8, 4 },
462 static const CostTblEntry<MVT> AVX2CostTbl[] = {
463 { ISD::SETCC, MVT::v4i64, 1 },
464 { ISD::SETCC, MVT::v8i32, 1 },
465 { ISD::SETCC, MVT::v16i16, 1 },
466 { ISD::SETCC, MVT::v32i8, 1 },
470 int Idx = CostTableLookup<MVT>(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
472 return LT.first * AVX2CostTbl[Idx].Cost;
476 int Idx = CostTableLookup<MVT>(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
478 return LT.first * AVX1CostTbl[Idx].Cost;
481 if (ST->hasSSE42()) {
482 int Idx = CostTableLookup<MVT>(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
484 return LT.first * SSE42CostTbl[Idx].Cost;
487 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
490 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
491 unsigned Index) const {
492 assert(Val->isVectorTy() && "This must be a vector type");
495 // Legalize the type.
496 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
498 // This type is legalized to a scalar type.
499 if (!LT.second.isVector())
502 // The type may be split. Normalize the index to the new type.
503 unsigned Width = LT.second.getVectorNumElements();
504 Index = Index % Width;
506 // Floating point scalars are already located in index #0.
507 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
511 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
514 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
515 unsigned AddressSpace) const {
516 // Legalize the type.
517 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
518 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
521 // Each load/store unit costs 1.
522 unsigned Cost = LT.first * 1;
524 // On Sandybridge 256bit load/stores are double pumped
525 // (but not on Haswell).
526 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())