lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MemoryObject.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "xcore-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// \brief A disassembler class for XCore.
  34 class XCoreDisassembler : public MCDisassembler {
  35 public:
  36   XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
  37     MCDisassembler(STI, Ctx) {}
  38
  39   /// \brief See MCDisassembler.
  40   virtual DecodeStatus getInstruction(MCInst &instr,
  41                                       uint64_t &size,
  42                                       const MemoryObject &region,
  43                                       uint64_t address,
  44                                       raw_ostream &vStream,
  45                                       raw_ostream &cStream) const override;
  46
  47 };
  48 }
  49
  50 static bool readInstruction16(const MemoryObject &region,
  51                               uint64_t address,
  52                               uint64_t &size,
  53                               uint16_t &insn) {
  54   uint8_t Bytes[4];
  55
  56   // We want to read exactly 2 Bytes of data.
  57   if (region.readBytes(address, 2, Bytes) == -1) {
  58     size = 0;
  59     return false;
  60   }
  61   // Encoded as a little-endian 16-bit word in the stream.
  62   insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
  63   return true;
  64 }
  65
  66 static bool readInstruction32(const MemoryObject &region,
  67                               uint64_t address,
  68                               uint64_t &size,
  69                               uint32_t &insn) {
  70   uint8_t Bytes[4];
  71
  72   // We want to read exactly 4 Bytes of data.
  73   if (region.readBytes(address, 4, Bytes) == -1) {
  74     size = 0;
  75     return false;
  76   }
  77   // Encoded as a little-endian 32-bit word in the stream.
  78   insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
  79          (Bytes[3] << 24);
  80   return true;
  81 }
  82
  83 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  84   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  85   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
  86   return *(RegInfo->getRegClass(RC).begin() + RegNo);
  87 }
  88
  89 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  90                                               unsigned RegNo,
  91                                               uint64_t Address,
  92                                               const void *Decoder);
  93
  94 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
  95                                              unsigned RegNo,
  96                                              uint64_t Address,
  97                                              const void *Decoder);
  98
  99 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 100                                       uint64_t Address, const void *Decoder);
 101
 102 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
 103                                         uint64_t Address, const void *Decoder);
 104
 105 static DecodeStatus Decode2RInstruction(MCInst &Inst,
 106                                         unsigned Insn,
 107                                         uint64_t Address,
 108                                         const void *Decoder);
 109
 110 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
 111                                            unsigned Insn,
 112                                            uint64_t Address,
 113                                            const void *Decoder);
 114
 115 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 116                                          unsigned Insn,
 117                                          uint64_t Address,
 118                                          const void *Decoder);
 119
 120 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 121                                               unsigned Insn,
 122                                               uint64_t Address,
 123                                               const void *Decoder);
 124
 125 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 126                                          unsigned Insn,
 127                                          uint64_t Address,
 128                                          const void *Decoder);
 129
 130 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 131                                              unsigned Insn,
 132                                              uint64_t Address,
 133                                              const void *Decoder);
 134
 135 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 136                                                    unsigned Insn,
 137                                                    uint64_t Address,
 138                                                    const void *Decoder);
 139
 140 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 141                                          unsigned Insn,
 142                                          uint64_t Address,
 143                                          const void *Decoder);
 144
 145 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 146                                           unsigned Insn,
 147                                           uint64_t Address,
 148                                           const void *Decoder);
 149
 150 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 151                                         unsigned Insn,
 152                                         uint64_t Address,
 153                                         const void *Decoder);
 154
 155 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
 156                                            unsigned Insn,
 157                                            uint64_t Address,
 158                                            const void *Decoder);
 159
 160 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 161                                           unsigned Insn,
 162                                           uint64_t Address,
 163                                           const void *Decoder);
 164
 165 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 166                                               unsigned Insn,
 167                                               uint64_t Address,
 168                                               const void *Decoder);
 169
 170 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
 171                                          unsigned Insn,
 172                                          uint64_t Address,
 173                                          const void *Decoder);
 174
 175 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
 176                                                unsigned Insn,
 177                                                uint64_t Address,
 178                                                const void *Decoder);
 179
 180 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
 181                                            unsigned Insn,
 182                                            uint64_t Address,
 183                                            const void *Decoder);
 184
 185 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
 186                                                unsigned Insn,
 187                                                uint64_t Address,
 188                                                const void *Decoder);
 189
 190 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
 191                                          unsigned Insn,
 192                                          uint64_t Address,
 193                                          const void *Decoder);
 194
 195 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
 196                                          unsigned Insn,
 197                                          uint64_t Address,
 198                                          const void *Decoder);
 199
 200 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
 201                                                unsigned Insn,
 202                                                uint64_t Address,
 203                                                const void *Decoder);
 204
 205 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
 206                                                      unsigned Insn,
 207                                                      uint64_t Address,
 208                                                      const void *Decoder);
 209
 210 #include "XCoreGenDisassemblerTables.inc"
 211
 212 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 213                                               unsigned RegNo,
 214                                               uint64_t Address,
 215                                               const void *Decoder)
 216 {
 217   if (RegNo > 11)
 218     return MCDisassembler::Fail;
 219   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 220   Inst.addOperand(MCOperand::CreateReg(Reg));
 221   return MCDisassembler::Success;
 222 }
 223
 224 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
 225                                              unsigned RegNo,
 226                                              uint64_t Address,
 227                                              const void *Decoder)
 228 {
 229   if (RegNo > 15)
 230     return MCDisassembler::Fail;
 231   unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
 232   Inst.addOperand(MCOperand::CreateReg(Reg));
 233   return MCDisassembler::Success;
 234 }
 235
 236 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 237                                       uint64_t Address, const void *Decoder) {
 238   if (Val > 11)
 239     return MCDisassembler::Fail;
 240   static unsigned Values[] = {
 241     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 242   };
 243   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 244   return MCDisassembler::Success;
 245 }
 246
 247 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
 248                                         uint64_t Address, const void *Decoder) {
 249   Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
 250   return MCDisassembler::Success;
 251 }
 252
 253 static DecodeStatus
 254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 255   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 256   if (Combined < 27)
 257     return MCDisassembler::Fail;
 258   if (fieldFromInstruction(Insn, 5, 1)) {
 259     if (Combined == 31)
 260       return MCDisassembler::Fail;
 261     Combined += 5;
 262   }
 263   Combined -= 27;
 264   unsigned Op1High = Combined % 3;
 265   unsigned Op2High = Combined / 3;
 266   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 267   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 268   return MCDisassembler::Success;
 269 }
 270
 271 static DecodeStatus
 272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 273                      unsigned &Op3) {
 274   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 275   if (Combined >= 27)
 276     return MCDisassembler::Fail;
 277
 278   unsigned Op1High = Combined % 3;
 279   unsigned Op2High = (Combined / 3) % 3;
 280   unsigned Op3High = Combined / 9;
 281   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 282   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 283   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 284   return MCDisassembler::Success;
 285 }
 286
 287 static DecodeStatus
 288 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 289                          const void *Decoder) {
 290   // Try and decode as a 3R instruction.
 291   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 292   switch (Opcode) {
 293   case 0x0:
 294     Inst.setOpcode(XCore::STW_2rus);
 295     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 296   case 0x1:
 297     Inst.setOpcode(XCore::LDW_2rus);
 298     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 299   case 0x2:
 300     Inst.setOpcode(XCore::ADD_3r);
 301     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 302   case 0x3:
 303     Inst.setOpcode(XCore::SUB_3r);
 304     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 305   case 0x4:
 306     Inst.setOpcode(XCore::SHL_3r);
 307     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 308   case 0x5:
 309     Inst.setOpcode(XCore::SHR_3r);
 310     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 311   case 0x6:
 312     Inst.setOpcode(XCore::EQ_3r);
 313     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 314   case 0x7:
 315     Inst.setOpcode(XCore::AND_3r);
 316     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 317   case 0x8:
 318     Inst.setOpcode(XCore::OR_3r);
 319     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 320   case 0x9:
 321     Inst.setOpcode(XCore::LDW_3r);
 322     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 323   case 0x10:
 324     Inst.setOpcode(XCore::LD16S_3r);
 325     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 326   case 0x11:
 327     Inst.setOpcode(XCore::LD8U_3r);
 328     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 329   case 0x12:
 330     Inst.setOpcode(XCore::ADD_2rus);
 331     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 332   case 0x13:
 333     Inst.setOpcode(XCore::SUB_2rus);
 334     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 335   case 0x14:
 336     Inst.setOpcode(XCore::SHL_2rus);
 337     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 338   case 0x15:
 339     Inst.setOpcode(XCore::SHR_2rus);
 340     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 341   case 0x16:
 342     Inst.setOpcode(XCore::EQ_2rus);
 343     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 344   case 0x17:
 345     Inst.setOpcode(XCore::TSETR_3r);
 346     return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
 347   case 0x18:
 348     Inst.setOpcode(XCore::LSS_3r);
 349     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 350   case 0x19:
 351     Inst.setOpcode(XCore::LSU_3r);
 352     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 353   }
 354   return MCDisassembler::Fail;
 355 }
 356
 357 static DecodeStatus
 358 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 359                     const void *Decoder) {
 360   unsigned Op1, Op2;
 361   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 362   if (S != MCDisassembler::Success)
 363     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 364
 365   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 366   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 367   return S;
 368 }
 369
 370 static DecodeStatus
 371 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 372                        const void *Decoder) {
 373   unsigned Op1, Op2;
 374   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 375   if (S != MCDisassembler::Success)
 376     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 377
 378   Inst.addOperand(MCOperand::CreateImm(Op1));
 379   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 380   return S;
 381 }
 382
 383 static DecodeStatus
 384 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 385                      const void *Decoder) {
 386   unsigned Op1, Op2;
 387   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 388   if (S != MCDisassembler::Success)
 389     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 390
 391   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 392   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 393   return S;
 394 }
 395
 396 static DecodeStatus
 397 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 398                           const void *Decoder) {
 399   unsigned Op1, Op2;
 400   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 401   if (S != MCDisassembler::Success)
 402     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 403
 404   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 405   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 406   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 407   return S;
 408 }
 409
 410 static DecodeStatus
 411 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 412                      const void *Decoder) {
 413   unsigned Op1, Op2;
 414   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 415   if (S != MCDisassembler::Success)
 416     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 417
 418   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 419   Inst.addOperand(MCOperand::CreateImm(Op2));
 420   return S;
 421 }
 422
 423 static DecodeStatus
 424 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 425                          const void *Decoder) {
 426   unsigned Op1, Op2;
 427   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 428   if (S != MCDisassembler::Success)
 429     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 430
 431   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 432   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 433   return S;
 434 }
 435
 436 static DecodeStatus
 437 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 438                                const void *Decoder) {
 439   unsigned Op1, Op2;
 440   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 441   if (S != MCDisassembler::Success)
 442     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 443
 444   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 445   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 446   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 447   return S;
 448 }
 449
 450 static DecodeStatus
 451 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 452                           const void *Decoder) {
 453   // Try and decode as a L3R / L2RUS instruction.
 454   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
 455                     fieldFromInstruction(Insn, 27, 5) << 4;
 456   switch (Opcode) {
 457   case 0x0c:
 458     Inst.setOpcode(XCore::STW_l3r);
 459     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 460   case 0x1c:
 461     Inst.setOpcode(XCore::XOR_l3r);
 462     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 463   case 0x2c:
 464     Inst.setOpcode(XCore::ASHR_l3r);
 465     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 466   case 0x3c:
 467     Inst.setOpcode(XCore::LDAWF_l3r);
 468     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 469   case 0x4c:
 470     Inst.setOpcode(XCore::LDAWB_l3r);
 471     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 472   case 0x5c:
 473     Inst.setOpcode(XCore::LDA16F_l3r);
 474     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 475   case 0x6c:
 476     Inst.setOpcode(XCore::LDA16B_l3r);
 477     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 478   case 0x7c:
 479     Inst.setOpcode(XCore::MUL_l3r);
 480     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 481   case 0x8c:
 482     Inst.setOpcode(XCore::DIVS_l3r);
 483     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 484   case 0x9c:
 485     Inst.setOpcode(XCore::DIVU_l3r);
 486     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 487   case 0x10c:
 488     Inst.setOpcode(XCore::ST16_l3r);
 489     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 490   case 0x11c:
 491     Inst.setOpcode(XCore::ST8_l3r);
 492     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 493   case 0x12c:
 494     Inst.setOpcode(XCore::ASHR_l2rus);
 495     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 496   case 0x12d:
 497     Inst.setOpcode(XCore::OUTPW_l2rus);
 498     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 499   case 0x12e:
 500     Inst.setOpcode(XCore::INPW_l2rus);
 501     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 502   case 0x13c:
 503     Inst.setOpcode(XCore::LDAWF_l2rus);
 504     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 505   case 0x14c:
 506     Inst.setOpcode(XCore::LDAWB_l2rus);
 507     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 508   case 0x15c:
 509     Inst.setOpcode(XCore::CRC_l3r);
 510     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
 511   case 0x18c:
 512     Inst.setOpcode(XCore::REMS_l3r);
 513     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 514   case 0x19c:
 515     Inst.setOpcode(XCore::REMU_l3r);
 516     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 517   }
 518   return MCDisassembler::Fail;
 519 }
 520
 521 static DecodeStatus
 522 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 523                                const void *Decoder) {
 524   unsigned Op1, Op2;
 525   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 526                                         Op1, Op2);
 527   if (S != MCDisassembler::Success)
 528     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 529
 530   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 531   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 532   return S;
 533 }
 534
 535 static DecodeStatus
 536 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 537                                const void *Decoder) {
 538   unsigned Op1, Op2;
 539   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 540                                         Op1, Op2);
 541   if (S != MCDisassembler::Success)
 542     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 543
 544   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 545   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 546   return S;
 547 }
 548
 549 static DecodeStatus
 550 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 551                     const void *Decoder) {
 552   unsigned Op1, Op2, Op3;
 553   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 554   if (S == MCDisassembler::Success) {
 555     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 556     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 557     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 558   }
 559   return S;
 560 }
 561
 562 static DecodeStatus
 563 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 564                        const void *Decoder) {
 565   unsigned Op1, Op2, Op3;
 566   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 567   if (S == MCDisassembler::Success) {
 568     Inst.addOperand(MCOperand::CreateImm(Op1));
 569     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 570     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 571   }
 572   return S;
 573 }
 574
 575 static DecodeStatus
 576 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 577                       const void *Decoder) {
 578   unsigned Op1, Op2, Op3;
 579   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 580   if (S == MCDisassembler::Success) {
 581     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 582     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 583     Inst.addOperand(MCOperand::CreateImm(Op3));
 584   }
 585   return S;
 586 }
 587
 588 static DecodeStatus
 589 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 590                       const void *Decoder) {
 591   unsigned Op1, Op2, Op3;
 592   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 593   if (S == MCDisassembler::Success) {
 594     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 595     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 596     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 597   }
 598   return S;
 599 }
 600
 601 static DecodeStatus
 602 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 603                      const void *Decoder) {
 604   unsigned Op1, Op2, Op3;
 605   DecodeStatus S =
 606     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 607   if (S == MCDisassembler::Success) {
 608     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 609     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 610     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 611   }
 612   return S;
 613 }
 614
 615 static DecodeStatus
 616 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 617                            const void *Decoder) {
 618   unsigned Op1, Op2, Op3;
 619   DecodeStatus S =
 620   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 621   if (S == MCDisassembler::Success) {
 622     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 623     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 624     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 625     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 626   }
 627   return S;
 628 }
 629
 630 static DecodeStatus
 631 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 632                        const void *Decoder) {
 633   unsigned Op1, Op2, Op3;
 634   DecodeStatus S =
 635   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 636   if (S == MCDisassembler::Success) {
 637     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 638     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 639     Inst.addOperand(MCOperand::CreateImm(Op3));
 640   }
 641   return S;
 642 }
 643
 644 static DecodeStatus
 645 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 646                            const void *Decoder) {
 647   unsigned Op1, Op2, Op3;
 648   DecodeStatus S =
 649   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 650   if (S == MCDisassembler::Success) {
 651     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 652     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 653     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 654   }
 655   return S;
 656 }
 657
 658 static DecodeStatus
 659 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 660                      const void *Decoder) {
 661   unsigned Op1, Op2, Op3, Op4, Op5, Op6;
 662   DecodeStatus S =
 663     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 664   if (S != MCDisassembler::Success)
 665     return S;
 666   S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
 667   if (S != MCDisassembler::Success)
 668     return S;
 669   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 670   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 671   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 672   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 673   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 674   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
 675   return S;
 676 }
 677
 678 static DecodeStatus
 679 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 680                      const void *Decoder) {
 681   // Try and decode as a L6R instruction.
 682   Inst.clear();
 683   unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
 684   switch (Opcode) {
 685   case 0x00:
 686     Inst.setOpcode(XCore::LMUL_l6r);
 687     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
 688   }
 689   return MCDisassembler::Fail;
 690 }
 691
 692 static DecodeStatus
 693 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 694                      const void *Decoder) {
 695   unsigned Op1, Op2, Op3, Op4, Op5;
 696   DecodeStatus S =
 697     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 698   if (S != MCDisassembler::Success)
 699     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 700   S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
 701   if (S != MCDisassembler::Success)
 702     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
 703
 704   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 705   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 706   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 707   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 708   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
 709   return S;
 710 }
 711
 712 static DecodeStatus
 713 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 714                            const void *Decoder) {
 715   unsigned Op1, Op2, Op3;
 716   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 717   DecodeStatus S =
 718     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 719   if (S == MCDisassembler::Success) {
 720     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 721     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 722   }
 723   if (S == MCDisassembler::Success) {
 724     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 725     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 726     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 727   }
 728   return S;
 729 }
 730
 731 static DecodeStatus
 732 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 733                                  const void *Decoder) {
 734   unsigned Op1, Op2, Op3;
 735   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
 736   DecodeStatus S =
 737   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 738   if (S == MCDisassembler::Success) {
 739     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 740     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 741   }
 742   if (S == MCDisassembler::Success) {
 743     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 744     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
 745     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 746     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 747   }
 748   return S;
 749 }
 750
 751 MCDisassembler::DecodeStatus
 752 XCoreDisassembler::getInstruction(MCInst &instr,
 753                                   uint64_t &Size,
 754                                   const MemoryObject &Region,
 755                                   uint64_t Address,
 756                                   raw_ostream &vStream,
 757                                   raw_ostream &cStream) const {
 758   uint16_t insn16;
 759
 760   if (!readInstruction16(Region, Address, Size, insn16)) {
 761     return Fail;
 762   }
 763
 764   // Calling the auto-generated decoder function.
 765   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 766                                           Address, this, STI);
 767   if (Result != Fail) {
 768     Size = 2;
 769     return Result;
 770   }
 771
 772   uint32_t insn32;
 773
 774   if (!readInstruction32(Region, Address, Size, insn32)) {
 775     return Fail;
 776   }
 777
 778   // Calling the auto-generated decoder function.
 779   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 780   if (Result != Fail) {
 781     Size = 4;
 782     return Result;
 783   }
 784
 785   return Fail;
 786 }
 787
 788 namespace llvm {
 789   extern Target TheXCoreTarget;
 790 }
 791
 792 static MCDisassembler *createXCoreDisassembler(const Target &T,
 793                                                const MCSubtargetInfo &STI,
 794                                                MCContext &Ctx) {
 795   return new XCoreDisassembler(STI, Ctx);
 796 }
 797
 798 extern "C" void LLVMInitializeXCoreDisassembler() {
 799   // Register the disassembler.
 800   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 801                                          createXCoreDisassembler);
 802 }