1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file is part of the XCore Disassembler.
13 //===----------------------------------------------------------------------===//
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MemoryObject.h"
23 #include "llvm/Support/TargetRegistry.h"
27 #define DEBUG_TYPE "xcore-disassembler"
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
33 /// \brief A disassembler class for XCore.
34 class XCoreDisassembler : public MCDisassembler {
36 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
37 MCDisassembler(STI, Ctx) {}
39 /// \brief See MCDisassembler.
40 virtual DecodeStatus getInstruction(MCInst &instr,
42 const MemoryObject ®ion,
45 raw_ostream &cStream) const;
50 static bool readInstruction16(const MemoryObject ®ion,
56 // We want to read exactly 2 Bytes of data.
57 if (region.readBytes(address, 2, Bytes) == -1) {
61 // Encoded as a little-endian 16-bit word in the stream.
62 insn = (Bytes[0] << 0) | (Bytes[1] << 8);
66 static bool readInstruction32(const MemoryObject ®ion,
72 // We want to read exactly 4 Bytes of data.
73 if (region.readBytes(address, 4, Bytes) == -1) {
77 // Encoded as a little-endian 32-bit word in the stream.
78 insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
83 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
84 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
85 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
86 return *(RegInfo->getRegClass(RC).begin() + RegNo);
89 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
94 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
99 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
100 uint64_t Address, const void *Decoder);
102 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
103 uint64_t Address, const void *Decoder);
105 static DecodeStatus Decode2RInstruction(MCInst &Inst,
108 const void *Decoder);
110 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
113 const void *Decoder);
115 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
118 const void *Decoder);
120 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
123 const void *Decoder);
125 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
128 const void *Decoder);
130 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
133 const void *Decoder);
135 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
138 const void *Decoder);
140 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
143 const void *Decoder);
145 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
148 const void *Decoder);
150 static DecodeStatus Decode3RInstruction(MCInst &Inst,
153 const void *Decoder);
155 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
158 const void *Decoder);
160 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
163 const void *Decoder);
165 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
168 const void *Decoder);
170 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
173 const void *Decoder);
175 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
178 const void *Decoder);
180 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
183 const void *Decoder);
185 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
188 const void *Decoder);
190 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
193 const void *Decoder);
195 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
198 const void *Decoder);
200 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
203 const void *Decoder);
205 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
208 const void *Decoder);
210 #include "XCoreGenDisassemblerTables.inc"
212 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
218 return MCDisassembler::Fail;
219 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
220 Inst.addOperand(MCOperand::CreateReg(Reg));
221 return MCDisassembler::Success;
224 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
230 return MCDisassembler::Fail;
231 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
232 Inst.addOperand(MCOperand::CreateReg(Reg));
233 return MCDisassembler::Success;
236 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder) {
239 return MCDisassembler::Fail;
240 static unsigned Values[] = {
241 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
243 Inst.addOperand(MCOperand::CreateImm(Values[Val]));
244 return MCDisassembler::Success;
247 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder) {
249 Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
250 return MCDisassembler::Success;
254 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
255 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
257 return MCDisassembler::Fail;
258 if (fieldFromInstruction(Insn, 5, 1)) {
260 return MCDisassembler::Fail;
264 unsigned Op1High = Combined % 3;
265 unsigned Op2High = Combined / 3;
266 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
267 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
268 return MCDisassembler::Success;
272 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
274 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
276 return MCDisassembler::Fail;
278 unsigned Op1High = Combined % 3;
279 unsigned Op2High = (Combined / 3) % 3;
280 unsigned Op3High = Combined / 9;
281 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
282 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
283 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
284 return MCDisassembler::Success;
288 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
289 const void *Decoder) {
290 // Try and decode as a 3R instruction.
291 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
294 Inst.setOpcode(XCore::STW_2rus);
295 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
297 Inst.setOpcode(XCore::LDW_2rus);
298 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
300 Inst.setOpcode(XCore::ADD_3r);
301 return Decode3RInstruction(Inst, Insn, Address, Decoder);
303 Inst.setOpcode(XCore::SUB_3r);
304 return Decode3RInstruction(Inst, Insn, Address, Decoder);
306 Inst.setOpcode(XCore::SHL_3r);
307 return Decode3RInstruction(Inst, Insn, Address, Decoder);
309 Inst.setOpcode(XCore::SHR_3r);
310 return Decode3RInstruction(Inst, Insn, Address, Decoder);
312 Inst.setOpcode(XCore::EQ_3r);
313 return Decode3RInstruction(Inst, Insn, Address, Decoder);
315 Inst.setOpcode(XCore::AND_3r);
316 return Decode3RInstruction(Inst, Insn, Address, Decoder);
318 Inst.setOpcode(XCore::OR_3r);
319 return Decode3RInstruction(Inst, Insn, Address, Decoder);
321 Inst.setOpcode(XCore::LDW_3r);
322 return Decode3RInstruction(Inst, Insn, Address, Decoder);
324 Inst.setOpcode(XCore::LD16S_3r);
325 return Decode3RInstruction(Inst, Insn, Address, Decoder);
327 Inst.setOpcode(XCore::LD8U_3r);
328 return Decode3RInstruction(Inst, Insn, Address, Decoder);
330 Inst.setOpcode(XCore::ADD_2rus);
331 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
333 Inst.setOpcode(XCore::SUB_2rus);
334 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
336 Inst.setOpcode(XCore::SHL_2rus);
337 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
339 Inst.setOpcode(XCore::SHR_2rus);
340 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
342 Inst.setOpcode(XCore::EQ_2rus);
343 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
345 Inst.setOpcode(XCore::TSETR_3r);
346 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
348 Inst.setOpcode(XCore::LSS_3r);
349 return Decode3RInstruction(Inst, Insn, Address, Decoder);
351 Inst.setOpcode(XCore::LSU_3r);
352 return Decode3RInstruction(Inst, Insn, Address, Decoder);
354 return MCDisassembler::Fail;
358 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
359 const void *Decoder) {
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
362 if (S != MCDisassembler::Success)
363 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
365 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
371 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
372 const void *Decoder) {
374 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
375 if (S != MCDisassembler::Success)
376 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
378 Inst.addOperand(MCOperand::CreateImm(Op1));
379 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
384 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
385 const void *Decoder) {
387 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
388 if (S != MCDisassembler::Success)
389 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
391 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
392 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
397 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
398 const void *Decoder) {
400 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
401 if (S != MCDisassembler::Success)
402 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
404 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
405 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
406 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
411 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
412 const void *Decoder) {
414 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
415 if (S != MCDisassembler::Success)
416 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
418 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
419 Inst.addOperand(MCOperand::CreateImm(Op2));
424 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
425 const void *Decoder) {
427 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
428 if (S != MCDisassembler::Success)
429 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
431 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
432 DecodeBitpOperand(Inst, Op2, Address, Decoder);
437 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
438 const void *Decoder) {
440 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
441 if (S != MCDisassembler::Success)
442 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
444 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
445 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
446 DecodeBitpOperand(Inst, Op2, Address, Decoder);
451 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
452 const void *Decoder) {
453 // Try and decode as a L3R / L2RUS instruction.
454 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
455 fieldFromInstruction(Insn, 27, 5) << 4;
458 Inst.setOpcode(XCore::STW_l3r);
459 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
461 Inst.setOpcode(XCore::XOR_l3r);
462 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
464 Inst.setOpcode(XCore::ASHR_l3r);
465 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
467 Inst.setOpcode(XCore::LDAWF_l3r);
468 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
470 Inst.setOpcode(XCore::LDAWB_l3r);
471 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
473 Inst.setOpcode(XCore::LDA16F_l3r);
474 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
476 Inst.setOpcode(XCore::LDA16B_l3r);
477 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
479 Inst.setOpcode(XCore::MUL_l3r);
480 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
482 Inst.setOpcode(XCore::DIVS_l3r);
483 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
485 Inst.setOpcode(XCore::DIVU_l3r);
486 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
488 Inst.setOpcode(XCore::ST16_l3r);
489 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
491 Inst.setOpcode(XCore::ST8_l3r);
492 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
494 Inst.setOpcode(XCore::ASHR_l2rus);
495 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
497 Inst.setOpcode(XCore::OUTPW_l2rus);
498 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
500 Inst.setOpcode(XCore::INPW_l2rus);
501 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
503 Inst.setOpcode(XCore::LDAWF_l2rus);
504 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
506 Inst.setOpcode(XCore::LDAWB_l2rus);
507 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
509 Inst.setOpcode(XCore::CRC_l3r);
510 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
512 Inst.setOpcode(XCore::REMS_l3r);
513 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
515 Inst.setOpcode(XCore::REMU_l3r);
516 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
518 return MCDisassembler::Fail;
522 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
523 const void *Decoder) {
525 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
527 if (S != MCDisassembler::Success)
528 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
530 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
531 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
536 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
537 const void *Decoder) {
539 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
541 if (S != MCDisassembler::Success)
542 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
544 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
545 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
550 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
551 const void *Decoder) {
552 unsigned Op1, Op2, Op3;
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
554 if (S == MCDisassembler::Success) {
555 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
556 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
563 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
564 const void *Decoder) {
565 unsigned Op1, Op2, Op3;
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
567 if (S == MCDisassembler::Success) {
568 Inst.addOperand(MCOperand::CreateImm(Op1));
569 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
570 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
576 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
577 const void *Decoder) {
578 unsigned Op1, Op2, Op3;
579 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
580 if (S == MCDisassembler::Success) {
581 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
582 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
583 Inst.addOperand(MCOperand::CreateImm(Op3));
589 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
590 const void *Decoder) {
591 unsigned Op1, Op2, Op3;
592 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
593 if (S == MCDisassembler::Success) {
594 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
595 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
596 DecodeBitpOperand(Inst, Op3, Address, Decoder);
602 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
603 const void *Decoder) {
604 unsigned Op1, Op2, Op3;
606 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
607 if (S == MCDisassembler::Success) {
608 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
609 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
610 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
616 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
617 const void *Decoder) {
618 unsigned Op1, Op2, Op3;
620 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
621 if (S == MCDisassembler::Success) {
622 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
623 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
624 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
625 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
631 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
632 const void *Decoder) {
633 unsigned Op1, Op2, Op3;
635 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
636 if (S == MCDisassembler::Success) {
637 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
638 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
639 Inst.addOperand(MCOperand::CreateImm(Op3));
645 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
646 const void *Decoder) {
647 unsigned Op1, Op2, Op3;
649 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
650 if (S == MCDisassembler::Success) {
651 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
652 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
653 DecodeBitpOperand(Inst, Op3, Address, Decoder);
659 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
660 const void *Decoder) {
661 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
663 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
664 if (S != MCDisassembler::Success)
666 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
667 if (S != MCDisassembler::Success)
669 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
670 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
671 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
672 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
673 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
674 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
679 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
680 const void *Decoder) {
681 // Try and decode as a L6R instruction.
683 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
686 Inst.setOpcode(XCore::LMUL_l6r);
687 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
689 return MCDisassembler::Fail;
693 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
694 const void *Decoder) {
695 unsigned Op1, Op2, Op3, Op4, Op5;
697 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
698 if (S != MCDisassembler::Success)
699 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
700 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
701 if (S != MCDisassembler::Success)
702 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
704 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
705 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
706 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
707 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
708 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
713 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
714 const void *Decoder) {
715 unsigned Op1, Op2, Op3;
716 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
718 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
719 if (S == MCDisassembler::Success) {
720 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
721 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
723 if (S == MCDisassembler::Success) {
724 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
725 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
726 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
732 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
733 const void *Decoder) {
734 unsigned Op1, Op2, Op3;
735 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
737 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
738 if (S == MCDisassembler::Success) {
739 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
740 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
742 if (S == MCDisassembler::Success) {
743 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
744 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
745 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
746 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
751 MCDisassembler::DecodeStatus
752 XCoreDisassembler::getInstruction(MCInst &instr,
754 const MemoryObject &Region,
756 raw_ostream &vStream,
757 raw_ostream &cStream) const {
760 if (!readInstruction16(Region, Address, Size, insn16)) {
764 // Calling the auto-generated decoder function.
765 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
767 if (Result != Fail) {
774 if (!readInstruction32(Region, Address, Size, insn32)) {
778 // Calling the auto-generated decoder function.
779 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
780 if (Result != Fail) {
789 extern Target TheXCoreTarget;
792 static MCDisassembler *createXCoreDisassembler(const Target &T,
793 const MCSubtargetInfo &STI,
795 return new XCoreDisassembler(STI, Ctx);
798 extern "C" void LLVMInitializeXCoreDisassembler() {
799 // Register the disassembler.
800 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
801 createXCoreDisassembler);