1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file is part of the XCore Disassembler.
13 //===----------------------------------------------------------------------===//
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/MemoryObject.h"
22 #include "llvm/Support/TargetRegistry.h"
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
30 /// \brief A disassembler class for XCore.
31 class XCoreDisassembler : public MCDisassembler {
32 const MCRegisterInfo *RegInfo;
34 XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
35 MCDisassembler(STI), RegInfo(Info) {}
37 /// \brief See MCDisassembler.
38 virtual DecodeStatus getInstruction(MCInst &instr,
40 const MemoryObject ®ion,
43 raw_ostream &cStream) const;
45 const MCRegisterInfo *getRegInfo() const { return RegInfo; }
49 static bool readInstruction16(const MemoryObject ®ion,
55 // We want to read exactly 2 Bytes of data.
56 if (region.readBytes(address, 2, Bytes, NULL) == -1) {
60 // Encoded as a little-endian 16-bit word in the stream.
61 insn = (Bytes[0] << 0) | (Bytes[1] << 8);
65 static bool readInstruction32(const MemoryObject ®ion,
71 // We want to read exactly 4 Bytes of data.
72 if (region.readBytes(address, 4, Bytes, NULL) == -1) {
76 // Encoded as a little-endian 32-bit word in the stream.
77 insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
83 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
84 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
93 uint64_t Address, const void *Decoder);
95 static DecodeStatus Decode2RInstruction(MCInst &Inst,
100 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
103 const void *Decoder);
105 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
108 const void *Decoder);
110 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
113 const void *Decoder);
115 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
118 const void *Decoder);
120 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
123 const void *Decoder);
125 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
128 const void *Decoder);
130 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
133 const void *Decoder);
135 static DecodeStatus Decode3RInstruction(MCInst &Inst,
138 const void *Decoder);
140 #include "XCoreGenDisassemblerTables.inc"
142 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
148 return MCDisassembler::Fail;
149 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
150 Inst.addOperand(MCOperand::CreateReg(Reg));
151 return MCDisassembler::Success;
154 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
155 uint64_t Address, const void *Decoder) {
157 return MCDisassembler::Fail;
158 static unsigned Values[] = {
159 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
161 Inst.addOperand(MCOperand::CreateImm(Values[Val]));
162 return MCDisassembler::Success;
166 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
167 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
169 return MCDisassembler::Fail;
170 if (fieldFromInstruction(Insn, 5, 1)) {
172 return MCDisassembler::Fail;
176 unsigned Op1High = Combined % 3;
177 unsigned Op2High = Combined / 3;
178 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
179 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
180 return MCDisassembler::Success;
184 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
186 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
188 return MCDisassembler::Fail;
190 unsigned Op1High = Combined % 3;
191 unsigned Op2High = (Combined / 3) % 3;
192 unsigned Op3High = Combined / 9;
193 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
194 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
195 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
196 return MCDisassembler::Success;
200 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
201 const void *Decoder) {
202 // Try and decode as a 3R instruction.
203 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
206 Inst.setOpcode(XCore::ADD_3r);
207 return Decode3RInstruction(Inst, Insn, Address, Decoder);
209 Inst.setOpcode(XCore::SUB_3r);
210 return Decode3RInstruction(Inst, Insn, Address, Decoder);
212 Inst.setOpcode(XCore::SHL_3r);
213 return Decode3RInstruction(Inst, Insn, Address, Decoder);
215 Inst.setOpcode(XCore::SHR_3r);
216 return Decode3RInstruction(Inst, Insn, Address, Decoder);
218 Inst.setOpcode(XCore::EQ_3r);
219 return Decode3RInstruction(Inst, Insn, Address, Decoder);
221 Inst.setOpcode(XCore::AND_3r);
222 return Decode3RInstruction(Inst, Insn, Address, Decoder);
224 Inst.setOpcode(XCore::OR_3r);
225 return Decode3RInstruction(Inst, Insn, Address, Decoder);
227 Inst.setOpcode(XCore::LDW_3r);
228 return Decode3RInstruction(Inst, Insn, Address, Decoder);
230 Inst.setOpcode(XCore::LD16S_3r);
231 return Decode3RInstruction(Inst, Insn, Address, Decoder);
233 Inst.setOpcode(XCore::LD8U_3r);
234 return Decode3RInstruction(Inst, Insn, Address, Decoder);
236 Inst.setOpcode(XCore::LSS_3r);
237 return Decode3RInstruction(Inst, Insn, Address, Decoder);
239 Inst.setOpcode(XCore::LSU_3r);
240 return Decode3RInstruction(Inst, Insn, Address, Decoder);
242 return MCDisassembler::Fail;
246 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
247 const void *Decoder) {
249 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
250 if (S != MCDisassembler::Success)
251 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
253 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
254 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
259 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
260 const void *Decoder) {
262 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
263 if (S != MCDisassembler::Success)
264 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
266 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
267 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
272 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
273 const void *Decoder) {
275 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
276 if (S != MCDisassembler::Success)
277 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
279 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
280 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
281 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
286 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
287 const void *Decoder) {
289 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
290 if (S != MCDisassembler::Success)
291 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
293 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
294 Inst.addOperand(MCOperand::CreateImm(Op2));
299 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
300 const void *Decoder) {
302 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
303 if (S != MCDisassembler::Success)
304 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
306 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
307 DecodeBitpOperand(Inst, Op2, Address, Decoder);
312 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
313 const void *Decoder) {
315 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
316 if (S != MCDisassembler::Success)
317 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
319 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
320 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
321 DecodeBitpOperand(Inst, Op2, Address, Decoder);
326 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
327 const void *Decoder) {
329 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
331 if (S == MCDisassembler::Success) {
332 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
333 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
339 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
340 const void *Decoder) {
342 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
344 if (S == MCDisassembler::Success) {
345 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
346 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
352 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
353 const void *Decoder) {
354 unsigned Op1, Op2, Op3;
355 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
356 if (S == MCDisassembler::Success) {
357 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
358 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
359 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
364 MCDisassembler::DecodeStatus
365 XCoreDisassembler::getInstruction(MCInst &instr,
367 const MemoryObject &Region,
369 raw_ostream &vStream,
370 raw_ostream &cStream) const {
373 if (!readInstruction16(Region, Address, Size, insn16)) {
377 // Calling the auto-generated decoder function.
378 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
380 if (Result != Fail) {
387 if (!readInstruction32(Region, Address, Size, insn32)) {
391 // Calling the auto-generated decoder function.
392 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
393 if (Result != Fail) {
402 extern Target TheXCoreTarget;
405 static MCDisassembler *createXCoreDisassembler(const Target &T,
406 const MCSubtargetInfo &STI) {
407 return new XCoreDisassembler(STI, T.createMCRegInfo(""));
410 extern "C" void LLVMInitializeXCoreDisassembler() {
411 // Register the disassembler.
412 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
413 createXCoreDisassembler);