lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 typedef MCDisassembler::DecodeStatus DecodeStatus;
  27
  28 namespace {
  29
  30 /// \brief A disassembler class for XCore.
  31 class XCoreDisassembler : public MCDisassembler {
  32   const MCRegisterInfo *RegInfo;
  33 public:
  34   XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
  35     MCDisassembler(STI), RegInfo(Info) {}
  36
  37   /// \brief See MCDisassembler.
  38   virtual DecodeStatus getInstruction(MCInst &instr,
  39                                       uint64_t &size,
  40                                       const MemoryObject &region,
  41                                       uint64_t address,
  42                                       raw_ostream &vStream,
  43                                       raw_ostream &cStream) const;
  44
  45   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  46 };
  47 }
  48
  49 static bool readInstruction16(const MemoryObject &region,
  50                               uint64_t address,
  51                               uint64_t &size,
  52                               uint16_t &insn) {
  53   uint8_t Bytes[4];
  54
  55   // We want to read exactly 2 Bytes of data.
  56   if (region.readBytes(address, 2, Bytes, NULL) == -1) {
  57     size = 0;
  58     return false;
  59   }
  60   // Encoded as a little-endian 16-bit word in the stream.
  61   insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
  62   return true;
  63 }
  64
  65 static bool readInstruction32(const MemoryObject &region,
  66                               uint64_t address,
  67                               uint64_t &size,
  68                               uint32_t &insn) {
  69   uint8_t Bytes[4];
  70
  71   // We want to read exactly 4 Bytes of data.
  72   if (region.readBytes(address, 4, Bytes, NULL) == -1) {
  73     size = 0;
  74     return false;
  75   }
  76   // Encoded as a little-endian 32-bit word in the stream.
  77   insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
  78          (Bytes[3] << 24);
  79   return true;
  80 }
  81
  82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  83   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  84   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
  85 }
  86
  87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  88                                               unsigned RegNo,
  89                                               uint64_t Address,
  90                                               const void *Decoder);
  91
  92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  93                                       uint64_t Address, const void *Decoder);
  94
  95 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
  96                                        uint64_t Address, const void *Decoder);
  97
  98 static DecodeStatus Decode2RInstruction(MCInst &Inst,
  99                                         unsigned Insn,
 100                                         uint64_t Address,
 101                                         const void *Decoder);
 102
 103 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 104                                          unsigned Insn,
 105                                          uint64_t Address,
 106                                          const void *Decoder);
 107
 108 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 109                                               unsigned Insn,
 110                                               uint64_t Address,
 111                                               const void *Decoder);
 112
 113 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 114                                          unsigned Insn,
 115                                          uint64_t Address,
 116                                          const void *Decoder);
 117
 118 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 119                                              unsigned Insn,
 120                                              uint64_t Address,
 121                                              const void *Decoder);
 122
 123 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 124                                                    unsigned Insn,
 125                                                    uint64_t Address,
 126                                                    const void *Decoder);
 127
 128 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 129                                          unsigned Insn,
 130                                          uint64_t Address,
 131                                          const void *Decoder);
 132
 133 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 134                                           unsigned Insn,
 135                                           uint64_t Address,
 136                                           const void *Decoder);
 137
 138 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 139                                         unsigned Insn,
 140                                         uint64_t Address,
 141                                         const void *Decoder);
 142
 143 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 144                                           unsigned Insn,
 145                                           uint64_t Address,
 146                                           const void *Decoder);
 147
 148 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
 154                                          unsigned Insn,
 155                                          uint64_t Address,
 156                                          const void *Decoder);
 157
 158 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
 159                                                unsigned Insn,
 160                                                uint64_t Address,
 161                                                const void *Decoder);
 162
 163 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
 164                                            unsigned Insn,
 165                                            uint64_t Address,
 166                                            const void *Decoder);
 167
 168 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
 169                                                unsigned Insn,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 #include "XCoreGenDisassemblerTables.inc"
 174
 175 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 176                                               unsigned RegNo,
 177                                               uint64_t Address,
 178                                               const void *Decoder)
 179 {
 180   if (RegNo > 11)
 181     return MCDisassembler::Fail;
 182   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 183   Inst.addOperand(MCOperand::CreateReg(Reg));
 184   return MCDisassembler::Success;
 185 }
 186
 187 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 188                                       uint64_t Address, const void *Decoder) {
 189   if (Val > 11)
 190     return MCDisassembler::Fail;
 191   static unsigned Values[] = {
 192     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 193   };
 194   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 195   return MCDisassembler::Success;
 196 }
 197
 198 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
 199                                        uint64_t Address, const void *Decoder) {
 200   Inst.addOperand(MCOperand::CreateImm(Val));
 201   Inst.addOperand(MCOperand::CreateImm(0));
 202   return MCDisassembler::Success;
 203 }
 204
 205 static DecodeStatus
 206 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 207   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 208   if (Combined < 27)
 209     return MCDisassembler::Fail;
 210   if (fieldFromInstruction(Insn, 5, 1)) {
 211     if (Combined == 31)
 212       return MCDisassembler::Fail;
 213     Combined += 5;
 214   }
 215   Combined -= 27;
 216   unsigned Op1High = Combined % 3;
 217   unsigned Op2High = Combined / 3;
 218   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 219   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 220   return MCDisassembler::Success;
 221 }
 222
 223 static DecodeStatus
 224 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 225                      unsigned &Op3) {
 226   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 227   if (Combined >= 27)
 228     return MCDisassembler::Fail;
 229
 230   unsigned Op1High = Combined % 3;
 231   unsigned Op2High = (Combined / 3) % 3;
 232   unsigned Op3High = Combined / 9;
 233   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 234   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 235   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 236   return MCDisassembler::Success;
 237 }
 238
 239 static DecodeStatus
 240 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 241                          const void *Decoder) {
 242   // Try and decode as a 3R instruction.
 243   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 244   switch (Opcode) {
 245   case 0x0:
 246     Inst.setOpcode(XCore::STW_2rus);
 247     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 248   case 0x1:
 249     Inst.setOpcode(XCore::LDW_2rus);
 250     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 251   case 0x2:
 252     Inst.setOpcode(XCore::ADD_3r);
 253     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 254   case 0x3:
 255     Inst.setOpcode(XCore::SUB_3r);
 256     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 257   case 0x4:
 258     Inst.setOpcode(XCore::SHL_3r);
 259     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 260   case 0x5:
 261     Inst.setOpcode(XCore::SHR_3r);
 262     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 263   case 0x6:
 264     Inst.setOpcode(XCore::EQ_3r);
 265     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 266   case 0x7:
 267     Inst.setOpcode(XCore::AND_3r);
 268     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 269   case 0x8:
 270     Inst.setOpcode(XCore::OR_3r);
 271     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 272   case 0x9:
 273     Inst.setOpcode(XCore::LDW_3r);
 274     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 275   case 0x10:
 276     Inst.setOpcode(XCore::LD16S_3r);
 277     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 278   case 0x11:
 279     Inst.setOpcode(XCore::LD8U_3r);
 280     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 281   case 0x12:
 282     Inst.setOpcode(XCore::ADD_2rus);
 283     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 284   case 0x13:
 285     Inst.setOpcode(XCore::SUB_2rus);
 286     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 287   case 0x14:
 288     Inst.setOpcode(XCore::SHL_2rus);
 289     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 290   case 0x15:
 291     Inst.setOpcode(XCore::SHR_2rus);
 292     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 293   case 0x16:
 294     Inst.setOpcode(XCore::EQ_2rus);
 295     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 296   case 0x18:
 297     Inst.setOpcode(XCore::LSS_3r);
 298     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 299   case 0x19:
 300     Inst.setOpcode(XCore::LSU_3r);
 301     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 302   }
 303   return MCDisassembler::Fail;
 304 }
 305
 306 static DecodeStatus
 307 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 308                     const void *Decoder) {
 309   unsigned Op1, Op2;
 310   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 311   if (S != MCDisassembler::Success)
 312     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 313
 314   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 315   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 316   return S;
 317 }
 318
 319 static DecodeStatus
 320 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 321                      const void *Decoder) {
 322   unsigned Op1, Op2;
 323   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 324   if (S != MCDisassembler::Success)
 325     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 326
 327   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 328   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 329   return S;
 330 }
 331
 332 static DecodeStatus
 333 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 334                           const void *Decoder) {
 335   unsigned Op1, Op2;
 336   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 337   if (S != MCDisassembler::Success)
 338     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 339
 340   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 341   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 342   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 343   return S;
 344 }
 345
 346 static DecodeStatus
 347 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 348                      const void *Decoder) {
 349   unsigned Op1, Op2;
 350   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 351   if (S != MCDisassembler::Success)
 352     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 353
 354   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 355   Inst.addOperand(MCOperand::CreateImm(Op2));
 356   return S;
 357 }
 358
 359 static DecodeStatus
 360 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 361                          const void *Decoder) {
 362   unsigned Op1, Op2;
 363   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 364   if (S != MCDisassembler::Success)
 365     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 366
 367   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 368   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 369   return S;
 370 }
 371
 372 static DecodeStatus
 373 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 374                                const void *Decoder) {
 375   unsigned Op1, Op2;
 376   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 377   if (S != MCDisassembler::Success)
 378     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 379
 380   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 381   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 382   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 383   return S;
 384 }
 385
 386 static DecodeStatus
 387 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 388                           const void *Decoder) {
 389   // Try and decode as a L3R / L2RUS instruction.
 390   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
 391                     fieldFromInstruction(Insn, 27, 5) << 4;
 392   switch (Opcode) {
 393   case 0x0c:
 394     Inst.setOpcode(XCore::STW_3r);
 395     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 396   case 0x1c:
 397     Inst.setOpcode(XCore::XOR_l3r);
 398     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 399   case 0x2c:
 400     Inst.setOpcode(XCore::ASHR_l3r);
 401     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 402   case 0x3c:
 403     Inst.setOpcode(XCore::LDAWF_l3r);
 404     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 405   case 0x4c:
 406     Inst.setOpcode(XCore::LDAWB_l3r);
 407     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 408   case 0x5c:
 409     Inst.setOpcode(XCore::LDA16F_l3r);
 410     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 411   case 0x6c:
 412     Inst.setOpcode(XCore::LDA16B_l3r);
 413     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 414   case 0x7c:
 415     Inst.setOpcode(XCore::MUL_l3r);
 416     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 417   case 0x8c:
 418     Inst.setOpcode(XCore::DIVS_l3r);
 419     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 420   case 0x9c:
 421     Inst.setOpcode(XCore::DIVU_l3r);
 422     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 423   case 0x10c:
 424     Inst.setOpcode(XCore::ST16_l3r);
 425     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 426   case 0x11c:
 427     Inst.setOpcode(XCore::ST8_l3r);
 428     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 429   case 0x12c:
 430     Inst.setOpcode(XCore::ASHR_l2rus);
 431     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 432   case 0x13c:
 433     Inst.setOpcode(XCore::LDAWF_l2rus);
 434     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 435   case 0x14c:
 436     Inst.setOpcode(XCore::LDAWB_l2rus);
 437     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 438   case 0x15c:
 439     Inst.setOpcode(XCore::CRC_l3r);
 440     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
 441   case 0x18c:
 442     Inst.setOpcode(XCore::REMS_l3r);
 443     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 444   case 0x19c:
 445     Inst.setOpcode(XCore::REMU_l3r);
 446     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 447   }
 448   return MCDisassembler::Fail;
 449 }
 450
 451 static DecodeStatus
 452 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 453                                const void *Decoder) {
 454   unsigned Op1, Op2;
 455   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 456                                         Op1, Op2);
 457   if (S != MCDisassembler::Success)
 458     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 459
 460   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 461   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 462   return S;
 463 }
 464
 465 static DecodeStatus
 466 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 467                                const void *Decoder) {
 468   unsigned Op1, Op2;
 469   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 470                                         Op1, Op2);
 471   if (S != MCDisassembler::Success)
 472     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 473
 474   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 475   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 476   return S;
 477 }
 478
 479 static DecodeStatus
 480 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 481                     const void *Decoder) {
 482   unsigned Op1, Op2, Op3;
 483   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 484   if (S == MCDisassembler::Success) {
 485     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 486     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 487     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 488   }
 489   return S;
 490 }
 491
 492 static DecodeStatus
 493 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 494                       const void *Decoder) {
 495   unsigned Op1, Op2, Op3;
 496   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 497   if (S == MCDisassembler::Success) {
 498     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 499     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 500     Inst.addOperand(MCOperand::CreateImm(Op3));
 501   }
 502   return S;
 503 }
 504
 505 static DecodeStatus
 506 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 507                       const void *Decoder) {
 508   unsigned Op1, Op2, Op3;
 509   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 510   if (S == MCDisassembler::Success) {
 511     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 512     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 513     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 514   }
 515   return S;
 516 }
 517
 518 static DecodeStatus
 519 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 520                      const void *Decoder) {
 521   unsigned Op1, Op2, Op3;
 522   DecodeStatus S =
 523     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 524   if (S == MCDisassembler::Success) {
 525     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 526     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 527     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 528   }
 529   return S;
 530 }
 531
 532 static DecodeStatus
 533 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 534                            const void *Decoder) {
 535   unsigned Op1, Op2, Op3;
 536   DecodeStatus S =
 537   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 538   if (S == MCDisassembler::Success) {
 539     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 540     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 541     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 542     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 543   }
 544   return S;
 545 }
 546
 547 static DecodeStatus
 548 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 549                        const void *Decoder) {
 550   unsigned Op1, Op2, Op3;
 551   DecodeStatus S =
 552   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 553   if (S == MCDisassembler::Success) {
 554     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 555     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 556     Inst.addOperand(MCOperand::CreateImm(Op3));
 557   }
 558   return S;
 559 }
 560
 561 static DecodeStatus
 562 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 563                            const void *Decoder) {
 564   unsigned Op1, Op2, Op3;
 565   DecodeStatus S =
 566   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 567   if (S == MCDisassembler::Success) {
 568     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 569     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 570     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 571   }
 572   return S;
 573 }
 574
 575 MCDisassembler::DecodeStatus
 576 XCoreDisassembler::getInstruction(MCInst &instr,
 577                                   uint64_t &Size,
 578                                   const MemoryObject &Region,
 579                                   uint64_t Address,
 580                                   raw_ostream &vStream,
 581                                   raw_ostream &cStream) const {
 582   uint16_t insn16;
 583
 584   if (!readInstruction16(Region, Address, Size, insn16)) {
 585     return Fail;
 586   }
 587
 588   // Calling the auto-generated decoder function.
 589   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 590                                           Address, this, STI);
 591   if (Result != Fail) {
 592     Size = 2;
 593     return Result;
 594   }
 595
 596   uint32_t insn32;
 597
 598   if (!readInstruction32(Region, Address, Size, insn32)) {
 599     return Fail;
 600   }
 601
 602   // Calling the auto-generated decoder function.
 603   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 604   if (Result != Fail) {
 605     Size = 4;
 606     return Result;
 607   }
 608
 609   return Fail;
 610 }
 611
 612 namespace llvm {
 613   extern Target TheXCoreTarget;
 614 }
 615
 616 static MCDisassembler *createXCoreDisassembler(const Target &T,
 617                                                const MCSubtargetInfo &STI) {
 618   return new XCoreDisassembler(STI, T.createMCRegInfo(""));
 619 }
 620
 621 extern "C" void LLVMInitializeXCoreDisassembler() {
 622   // Register the disassembler.
 623   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 624                                          createXCoreDisassembler);
 625 }