1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file is part of the XCore Disassembler.
13 //===----------------------------------------------------------------------===//
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/Support/MemoryObject.h"
22 #include "llvm/Support/TargetRegistry.h"
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
30 /// \brief A disassembler class for XCore.
31 class XCoreDisassembler : public MCDisassembler {
32 const MCRegisterInfo *RegInfo;
34 XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
35 MCDisassembler(STI), RegInfo(Info) {}
37 /// \brief See MCDisassembler.
38 virtual DecodeStatus getInstruction(MCInst &instr,
40 const MemoryObject ®ion,
43 raw_ostream &cStream) const;
45 const MCRegisterInfo *getRegInfo() const { return RegInfo; }
49 static bool readInstruction16(const MemoryObject ®ion,
55 // We want to read exactly 2 Bytes of data.
56 if (region.readBytes(address, 2, Bytes, NULL) == -1) {
60 // Encoded as a little-endian 16-bit word in the stream.
61 insn = (Bytes[0] << 0) | (Bytes[1] << 8);
65 static bool readInstruction32(const MemoryObject ®ion,
71 // We want to read exactly 4 Bytes of data.
72 if (region.readBytes(address, 4, Bytes, NULL) == -1) {
76 // Encoded as a little-endian 32-bit word in the stream.
77 insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
83 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
84 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
93 uint64_t Address, const void *Decoder);
95 static DecodeStatus Decode2RInstruction(MCInst &Inst,
100 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
103 const void *Decoder);
105 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
108 const void *Decoder);
110 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
113 const void *Decoder);
115 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
118 const void *Decoder);
120 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
123 const void *Decoder);
125 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
128 const void *Decoder);
130 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
133 const void *Decoder);
135 #include "XCoreGenDisassemblerTables.inc"
137 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
143 return MCDisassembler::Fail;
144 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
145 Inst.addOperand(MCOperand::CreateReg(Reg));
146 return MCDisassembler::Success;
149 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
150 uint64_t Address, const void *Decoder) {
152 return MCDisassembler::Fail;
153 static unsigned Values[] = {
154 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
156 Inst.addOperand(MCOperand::CreateImm(Values[Val]));
157 return MCDisassembler::Success;
161 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
162 unsigned Combined = fieldFromInstruction(Insn, 6, 5) +
163 fieldFromInstruction(Insn, 5, 1) * 5 - 27;
165 return MCDisassembler::Fail;
167 unsigned Op1High = Combined % 3;
168 unsigned Op2High = Combined / 3;
169 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
170 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
171 return MCDisassembler::Success;
175 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
176 const void *Decoder) {
178 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
179 if (S == MCDisassembler::Success) {
180 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
181 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
187 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
188 const void *Decoder) {
190 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
191 if (S == MCDisassembler::Success) {
192 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
193 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
199 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
200 const void *Decoder) {
202 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
203 if (S == MCDisassembler::Success) {
204 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
205 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
206 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
212 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
213 const void *Decoder) {
215 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
216 if (S == MCDisassembler::Success) {
217 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
218 Inst.addOperand(MCOperand::CreateImm(Op2));
224 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
225 const void *Decoder) {
227 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
228 if (S == MCDisassembler::Success) {
229 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
230 DecodeBitpOperand(Inst, Op2, Address, Decoder);
236 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
237 const void *Decoder) {
239 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
240 if (S == MCDisassembler::Success) {
241 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
242 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
243 DecodeBitpOperand(Inst, Op2, Address, Decoder);
249 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
250 const void *Decoder) {
252 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
254 if (S == MCDisassembler::Success) {
255 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
256 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
262 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
263 const void *Decoder) {
265 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
267 if (S == MCDisassembler::Success) {
268 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
269 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
274 MCDisassembler::DecodeStatus
275 XCoreDisassembler::getInstruction(MCInst &instr,
277 const MemoryObject &Region,
279 raw_ostream &vStream,
280 raw_ostream &cStream) const {
283 if (!readInstruction16(Region, Address, Size, insn16)) {
287 // Calling the auto-generated decoder function.
288 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
290 if (Result != Fail) {
297 if (!readInstruction32(Region, Address, Size, insn32)) {
301 // Calling the auto-generated decoder function.
302 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
303 if (Result != Fail) {
312 extern Target TheXCoreTarget;
315 static MCDisassembler *createXCoreDisassembler(const Target &T,
316 const MCSubtargetInfo &STI) {
317 return new XCoreDisassembler(STI, T.createMCRegInfo(""));
320 extern "C" void LLVMInitializeXCoreDisassembler() {
321 // Register the disassembler.
322 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
323 createXCoreDisassembler);