1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file is part of the XCore Disassembler.
13 //===----------------------------------------------------------------------===//
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/TargetRegistry.h"
26 #define DEBUG_TYPE "xcore-disassembler"
28 typedef MCDisassembler::DecodeStatus DecodeStatus;
32 /// \brief A disassembler class for XCore.
33 class XCoreDisassembler : public MCDisassembler {
35 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
36 MCDisassembler(STI, Ctx) {}
38 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39 ArrayRef<uint8_t> Bytes, uint64_t Address,
41 raw_ostream &CStream) const override;
45 static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
46 uint64_t &Size, uint16_t &Insn) {
47 // We want to read exactly 2 Bytes of data.
48 if (Bytes.size() < 2) {
52 // Encoded as a little-endian 16-bit word in the stream.
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
57 static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
58 uint64_t &Size, uint32_t &Insn) {
59 // We want to read exactly 4 Bytes of data.
60 if (Bytes.size() < 4) {
64 // Encoded as a little-endian 32-bit word in the stream.
66 (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
70 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
71 const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
72 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
73 return *(RegInfo->getRegClass(RC).begin() + RegNo);
76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
87 uint64_t Address, const void *Decoder);
89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
90 uint64_t Address, const void *Decoder);
92 static DecodeStatus Decode2RInstruction(MCInst &Inst,
97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
100 const void *Decoder);
102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
105 const void *Decoder);
107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
110 const void *Decoder);
112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
115 const void *Decoder);
117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
120 const void *Decoder);
122 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
125 const void *Decoder);
127 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
130 const void *Decoder);
132 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
135 const void *Decoder);
137 static DecodeStatus Decode3RInstruction(MCInst &Inst,
140 const void *Decoder);
142 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
145 const void *Decoder);
147 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
150 const void *Decoder);
152 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
155 const void *Decoder);
157 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
160 const void *Decoder);
162 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
165 const void *Decoder);
167 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
170 const void *Decoder);
172 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
175 const void *Decoder);
177 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
180 const void *Decoder);
182 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
185 const void *Decoder);
187 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
190 const void *Decoder);
192 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
195 const void *Decoder);
197 #include "XCoreGenDisassemblerTables.inc"
199 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
205 return MCDisassembler::Fail;
206 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
207 Inst.addOperand(MCOperand::createReg(Reg));
208 return MCDisassembler::Success;
211 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
217 return MCDisassembler::Fail;
218 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
219 Inst.addOperand(MCOperand::createReg(Reg));
220 return MCDisassembler::Success;
223 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder) {
226 return MCDisassembler::Fail;
227 static unsigned Values[] = {
228 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
230 Inst.addOperand(MCOperand::createImm(Values[Val]));
231 return MCDisassembler::Success;
234 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder) {
236 Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
237 return MCDisassembler::Success;
241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
242 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
244 return MCDisassembler::Fail;
245 if (fieldFromInstruction(Insn, 5, 1)) {
247 return MCDisassembler::Fail;
251 unsigned Op1High = Combined % 3;
252 unsigned Op2High = Combined / 3;
253 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
255 return MCDisassembler::Success;
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
261 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
263 return MCDisassembler::Fail;
265 unsigned Op1High = Combined % 3;
266 unsigned Op2High = (Combined / 3) % 3;
267 unsigned Op3High = Combined / 9;
268 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
271 return MCDisassembler::Success;
275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
276 const void *Decoder) {
277 // Try and decode as a 3R instruction.
278 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
281 Inst.setOpcode(XCore::STW_2rus);
282 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
284 Inst.setOpcode(XCore::LDW_2rus);
285 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
287 Inst.setOpcode(XCore::ADD_3r);
288 return Decode3RInstruction(Inst, Insn, Address, Decoder);
290 Inst.setOpcode(XCore::SUB_3r);
291 return Decode3RInstruction(Inst, Insn, Address, Decoder);
293 Inst.setOpcode(XCore::SHL_3r);
294 return Decode3RInstruction(Inst, Insn, Address, Decoder);
296 Inst.setOpcode(XCore::SHR_3r);
297 return Decode3RInstruction(Inst, Insn, Address, Decoder);
299 Inst.setOpcode(XCore::EQ_3r);
300 return Decode3RInstruction(Inst, Insn, Address, Decoder);
302 Inst.setOpcode(XCore::AND_3r);
303 return Decode3RInstruction(Inst, Insn, Address, Decoder);
305 Inst.setOpcode(XCore::OR_3r);
306 return Decode3RInstruction(Inst, Insn, Address, Decoder);
308 Inst.setOpcode(XCore::LDW_3r);
309 return Decode3RInstruction(Inst, Insn, Address, Decoder);
311 Inst.setOpcode(XCore::LD16S_3r);
312 return Decode3RInstruction(Inst, Insn, Address, Decoder);
314 Inst.setOpcode(XCore::LD8U_3r);
315 return Decode3RInstruction(Inst, Insn, Address, Decoder);
317 Inst.setOpcode(XCore::ADD_2rus);
318 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
320 Inst.setOpcode(XCore::SUB_2rus);
321 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
323 Inst.setOpcode(XCore::SHL_2rus);
324 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
326 Inst.setOpcode(XCore::SHR_2rus);
327 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
329 Inst.setOpcode(XCore::EQ_2rus);
330 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
332 Inst.setOpcode(XCore::TSETR_3r);
333 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
335 Inst.setOpcode(XCore::LSS_3r);
336 return Decode3RInstruction(Inst, Insn, Address, Decoder);
338 Inst.setOpcode(XCore::LSU_3r);
339 return Decode3RInstruction(Inst, Insn, Address, Decoder);
341 return MCDisassembler::Fail;
345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
346 const void *Decoder) {
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
349 if (S != MCDisassembler::Success)
350 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
352 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
359 const void *Decoder) {
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
362 if (S != MCDisassembler::Success)
363 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
365 Inst.addOperand(MCOperand::createImm(Op1));
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
372 const void *Decoder) {
374 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
375 if (S != MCDisassembler::Success)
376 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
378 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
379 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
385 const void *Decoder) {
387 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
388 if (S != MCDisassembler::Success)
389 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
391 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
392 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
393 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
399 const void *Decoder) {
401 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
402 if (S != MCDisassembler::Success)
403 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
405 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
406 Inst.addOperand(MCOperand::createImm(Op2));
411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
412 const void *Decoder) {
414 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
415 if (S != MCDisassembler::Success)
416 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
418 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
419 DecodeBitpOperand(Inst, Op2, Address, Decoder);
424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
425 const void *Decoder) {
427 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
428 if (S != MCDisassembler::Success)
429 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
431 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
432 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
433 DecodeBitpOperand(Inst, Op2, Address, Decoder);
438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
439 const void *Decoder) {
440 // Try and decode as a L3R / L2RUS instruction.
441 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
442 fieldFromInstruction(Insn, 27, 5) << 4;
445 Inst.setOpcode(XCore::STW_l3r);
446 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
448 Inst.setOpcode(XCore::XOR_l3r);
449 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
451 Inst.setOpcode(XCore::ASHR_l3r);
452 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
454 Inst.setOpcode(XCore::LDAWF_l3r);
455 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
457 Inst.setOpcode(XCore::LDAWB_l3r);
458 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
460 Inst.setOpcode(XCore::LDA16F_l3r);
461 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
463 Inst.setOpcode(XCore::LDA16B_l3r);
464 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
466 Inst.setOpcode(XCore::MUL_l3r);
467 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
469 Inst.setOpcode(XCore::DIVS_l3r);
470 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
472 Inst.setOpcode(XCore::DIVU_l3r);
473 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
475 Inst.setOpcode(XCore::ST16_l3r);
476 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
478 Inst.setOpcode(XCore::ST8_l3r);
479 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
481 Inst.setOpcode(XCore::ASHR_l2rus);
482 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
484 Inst.setOpcode(XCore::OUTPW_l2rus);
485 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
487 Inst.setOpcode(XCore::INPW_l2rus);
488 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
490 Inst.setOpcode(XCore::LDAWF_l2rus);
491 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
493 Inst.setOpcode(XCore::LDAWB_l2rus);
494 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
496 Inst.setOpcode(XCore::CRC_l3r);
497 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
499 Inst.setOpcode(XCore::REMS_l3r);
500 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
502 Inst.setOpcode(XCore::REMU_l3r);
503 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
505 return MCDisassembler::Fail;
509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
510 const void *Decoder) {
512 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
514 if (S != MCDisassembler::Success)
515 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
517 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
518 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
524 const void *Decoder) {
526 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
528 if (S != MCDisassembler::Success)
529 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
531 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
532 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
538 const void *Decoder) {
539 unsigned Op1, Op2, Op3;
540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
541 if (S == MCDisassembler::Success) {
542 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
543 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
551 const void *Decoder) {
552 unsigned Op1, Op2, Op3;
553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
554 if (S == MCDisassembler::Success) {
555 Inst.addOperand(MCOperand::createImm(Op1));
556 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
564 const void *Decoder) {
565 unsigned Op1, Op2, Op3;
566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
567 if (S == MCDisassembler::Success) {
568 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
569 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
570 Inst.addOperand(MCOperand::createImm(Op3));
576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
577 const void *Decoder) {
578 unsigned Op1, Op2, Op3;
579 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
580 if (S == MCDisassembler::Success) {
581 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
582 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
583 DecodeBitpOperand(Inst, Op3, Address, Decoder);
589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
590 const void *Decoder) {
591 unsigned Op1, Op2, Op3;
593 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
594 if (S == MCDisassembler::Success) {
595 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
596 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
597 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
604 const void *Decoder) {
605 unsigned Op1, Op2, Op3;
607 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
608 if (S == MCDisassembler::Success) {
609 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
610 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
611 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
612 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
619 const void *Decoder) {
620 unsigned Op1, Op2, Op3;
622 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
623 if (S == MCDisassembler::Success) {
624 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
625 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
626 Inst.addOperand(MCOperand::createImm(Op3));
632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
633 const void *Decoder) {
634 unsigned Op1, Op2, Op3;
636 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
637 if (S == MCDisassembler::Success) {
638 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
639 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
640 DecodeBitpOperand(Inst, Op3, Address, Decoder);
646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
647 const void *Decoder) {
648 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
650 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
651 if (S != MCDisassembler::Success)
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
654 if (S != MCDisassembler::Success)
656 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
658 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
659 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
660 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
661 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
667 const void *Decoder) {
668 // Try and decode as a L6R instruction.
670 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
673 Inst.setOpcode(XCore::LMUL_l6r);
674 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
676 return MCDisassembler::Fail;
680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
681 const void *Decoder) {
682 unsigned Op1, Op2, Op3, Op4, Op5;
684 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
685 if (S != MCDisassembler::Success)
686 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
688 if (S != MCDisassembler::Success)
689 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
691 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
693 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
694 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
695 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
701 const void *Decoder) {
702 unsigned Op1, Op2, Op3;
703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
705 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
706 if (S == MCDisassembler::Success) {
707 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
710 if (S == MCDisassembler::Success) {
711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
712 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
713 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
720 const void *Decoder) {
721 unsigned Op1, Op2, Op3;
722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
724 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
725 if (S == MCDisassembler::Success) {
726 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
727 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
729 if (S == MCDisassembler::Success) {
730 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
731 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
732 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
733 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
738 MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(
739 MCInst &instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
740 raw_ostream &vStream, raw_ostream &cStream) const {
743 if (!readInstruction16(Bytes, Address, Size, insn16)) {
747 // Calling the auto-generated decoder function.
748 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
750 if (Result != Fail) {
757 if (!readInstruction32(Bytes, Address, Size, insn32)) {
761 // Calling the auto-generated decoder function.
762 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
763 if (Result != Fail) {
772 extern Target TheXCoreTarget;
775 static MCDisassembler *createXCoreDisassembler(const Target &T,
776 const MCSubtargetInfo &STI,
778 return new XCoreDisassembler(STI, Ctx);
781 extern "C" void LLVMInitializeXCoreDisassembler() {
782 // Register the disassembler.
783 TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
784 createXCoreDisassembler);