Reintroduce support for overloading target intrinsics
[oota-llvm.git] / lib / Target / XCore / XCore.td
1 //===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
16
17 include "llvm/Target/Target.td"
18
19 //===----------------------------------------------------------------------===//
20 // Descriptions
21 //===----------------------------------------------------------------------===//
22
23 include "XCoreRegisterInfo.td"
24 include "XCoreInstrInfo.td"
25 include "XCoreCallingConv.td"
26
27 def XCoreInstrInfo : InstrInfo {
28   let TSFlagsFields = [];
29   let TSFlagsShifts = [];
30 }
31
32 //===----------------------------------------------------------------------===//
33 // XCore processors supported.
34 //===----------------------------------------------------------------------===//
35
36 class Proc<string Name, list<SubtargetFeature> Features>
37  : Processor<Name, NoItineraries, Features>;
38
39 def : Proc<"generic",      []>;
40 def : Proc<"xs1b-generic", []>;
41
42 //===----------------------------------------------------------------------===//
43 // Declare the target which we are implementing
44 //===----------------------------------------------------------------------===//
45
46 def XCore : Target {
47   // Pull in Instruction Info:
48   let InstructionSet = XCoreInstrInfo;
49 }