1 //===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains XCore frame information that doesn't fit anywhere else
13 //===----------------------------------------------------------------------===//
15 #include "XCoreFrameLowering.h"
17 #include "XCoreInstrInfo.h"
18 #include "XCoreMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include <algorithm> // std::sort
34 static const unsigned FramePtr = XCore::R10;
35 static const int MaxImmU16 = (1<<16) - 1;
37 // helper functions. FIXME: Eliminate.
38 static inline bool isImmU6(unsigned val) {
39 return val < (1 << 6);
42 static inline bool isImmU16(unsigned val) {
43 return val < (1 << 16);
46 // Helper structure with compare function for handling stack slots.
48 struct StackSlotInfo {
52 StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){};
54 } // end anonymous namespace
56 static bool CompareSSIOffset(const StackSlotInfo& a, const StackSlotInfo& b) {
57 return a.Offset < b.Offset;
61 static void EmitDefCfaRegister(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI, DebugLoc dl,
63 const TargetInstrInfo &TII,
64 MachineModuleInfo *MMI, unsigned DRegNum) {
65 unsigned CFIIndex = MMI->addFrameInst(
66 MCCFIInstruction::createDefCfaRegister(nullptr, DRegNum));
67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
68 .addCFIIndex(CFIIndex);
71 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MBBI, DebugLoc dl,
73 const TargetInstrInfo &TII,
74 MachineModuleInfo *MMI, int Offset) {
76 MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
78 .addCFIIndex(CFIIndex);
81 static void EmitCfiOffset(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MBBI, DebugLoc dl,
83 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
84 unsigned DRegNum, int Offset) {
85 unsigned CFIIndex = MMI->addFrameInst(
86 MCCFIInstruction::createOffset(nullptr, DRegNum, Offset));
87 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
88 .addCFIIndex(CFIIndex);
91 /// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the
92 /// frame. During these steps, it may be necessary to spill registers.
93 /// IfNeededExtSP emits the necessary EXTSP instructions to move the SP only
94 /// as far as to make 'OffsetFromBottom' reachable using an STWSP_lru6.
95 /// \param OffsetFromTop the spill offset from the top of the frame.
96 /// \param [in,out] Adjusted the current SP offset from the top of the frame.
97 static void IfNeededExtSP(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MBBI, DebugLoc dl,
99 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
100 int OffsetFromTop, int &Adjusted, int FrameSize,
101 bool emitFrameMoves) {
102 while (OffsetFromTop > Adjusted) {
103 assert(Adjusted < FrameSize && "OffsetFromTop is beyond FrameSize");
104 int remaining = FrameSize - Adjusted;
105 int OpImm = (remaining > MaxImmU16) ? MaxImmU16 : remaining;
106 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
110 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
114 /// The SP register is moved in steps of 'MaxImmU16' towards the top of the
115 /// frame. During these steps, it may be necessary to re-load registers.
116 /// IfNeededLDAWSP emits the necessary LDAWSP instructions to move the SP only
117 /// as far as to make 'OffsetFromTop' reachable using an LDAWSP_lru6.
118 /// \param OffsetFromTop the spill offset from the top of the frame.
119 /// \param [in,out] RemainingAdj the current SP offset from the top of the
121 static void IfNeededLDAWSP(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator MBBI, DebugLoc dl,
123 const TargetInstrInfo &TII, int OffsetFromTop,
125 while (OffsetFromTop < RemainingAdj - MaxImmU16) {
126 assert(RemainingAdj && "OffsetFromTop is beyond FrameSize");
127 int OpImm = (RemainingAdj > MaxImmU16) ? MaxImmU16 : RemainingAdj;
128 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
130 RemainingAdj -= OpImm;
134 /// Creates an ordered list of registers that are spilled
135 /// during the emitPrologue/emitEpilogue.
136 /// Registers are ordered according to their frame offset.
137 /// As offsets are negative, the largest offsets will be first.
138 static void GetSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
139 MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
140 bool fetchLR, bool fetchFP) {
142 int Offset = MFI->getObjectOffset(XFI->getLRSpillSlot());
143 SpillList.push_back(StackSlotInfo(XFI->getLRSpillSlot(),
148 int Offset = MFI->getObjectOffset(XFI->getFPSpillSlot());
149 SpillList.push_back(StackSlotInfo(XFI->getFPSpillSlot(),
153 std::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
156 /// Creates an ordered list of EH info register 'spills'.
157 /// These slots are only used by the unwinder and calls to llvm.eh.return().
158 /// Registers are ordered according to their frame offset.
159 /// As offsets are negative, the largest offsets will be first.
160 static void GetEHSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
161 MachineFrameInfo *MFI, XCoreFunctionInfo *XFI,
162 const TargetLowering *TL) {
163 assert(XFI->hasEHSpillSlot() && "There are no EH register spill slots");
164 const int* EHSlot = XFI->getEHSpillSlot();
165 SpillList.push_back(StackSlotInfo(EHSlot[0],
166 MFI->getObjectOffset(EHSlot[0]),
167 TL->getExceptionPointerRegister()));
168 SpillList.push_back(StackSlotInfo(EHSlot[0],
169 MFI->getObjectOffset(EHSlot[1]),
170 TL->getExceptionSelectorRegister()));
171 std::sort(SpillList.begin(), SpillList.end(), CompareSSIOffset);
175 static MachineMemOperand *
176 getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, unsigned flags) {
177 MachineFunction *MF = MBB.getParent();
178 const MachineFrameInfo &MFI = *MF->getFrameInfo();
179 MachineMemOperand *MMO =
180 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
181 flags, MFI.getObjectSize(FrameIndex),
182 MFI.getObjectAlignment(FrameIndex));
187 /// Restore clobbered registers with their spill slot value.
188 /// The SP will be adjusted at the same time, thus the SpillList must be ordered
189 /// with the largest (negative) offsets first.
191 RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
192 DebugLoc dl, const TargetInstrInfo &TII, int &RemainingAdj,
193 SmallVectorImpl<StackSlotInfo> &SpillList) {
194 for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
195 assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
196 assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
197 int OffsetFromTop = - SpillList[i].Offset/4;
198 IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
199 int Offset = RemainingAdj - OffsetFromTop;
200 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
201 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
203 .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
204 MachineMemOperand::MOLoad));
208 //===----------------------------------------------------------------------===//
209 // XCoreFrameLowering:
210 //===----------------------------------------------------------------------===//
212 XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
213 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0) {
217 bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
218 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
219 MF.getFrameInfo()->hasVarSizedObjects();
222 void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
223 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
224 MachineBasicBlock::iterator MBBI = MBB.begin();
225 MachineFrameInfo *MFI = MF.getFrameInfo();
226 MachineModuleInfo *MMI = &MF.getMMI();
227 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
228 const XCoreInstrInfo &TII =
229 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
230 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
231 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
233 if (MFI->getMaxAlignment() > getStackAlignment())
234 report_fatal_error("emitPrologue unsupported alignment: "
235 + Twine(MFI->getMaxAlignment()));
237 const AttributeSet &PAL = MF.getFunction()->getAttributes();
238 if (PAL.hasAttrSomewhere(Attribute::Nest))
239 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
240 // FIX: Needs addMemOperand() but can't use getFixedStack() or getStack().
242 // Work out frame sizes.
243 // We will adjust the SP in stages towards the final FrameSize.
244 assert(MFI->getStackSize()%4 == 0 && "Misaligned frame size");
245 const int FrameSize = MFI->getStackSize() / 4;
248 bool saveLR = XFI->hasLRSpillSlot();
249 bool UseENTSP = saveLR && FrameSize
250 && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
254 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
257 // Allocate space on the stack at the same time as saving LR.
258 Adjusted = (FrameSize > MaxImmU16) ? MaxImmU16 : FrameSize;
259 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
260 MBB.addLiveIn(XCore::LR);
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
262 MIB.addImm(Adjusted);
263 MIB->addRegisterKilled(XCore::LR, MF.getTarget().getRegisterInfo(), true);
264 if (emitFrameMoves) {
265 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
266 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
267 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, 0);
271 // If necessary, save LR and FP to the stack, as we EXTSP.
272 SmallVector<StackSlotInfo,2> SpillList;
273 GetSpillList(SpillList, MFI, XFI, saveLR, FP);
274 // We want the nearest (negative) offsets first, so reverse list.
275 std::reverse(SpillList.begin(), SpillList.end());
276 for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
277 assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
278 assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
279 int OffsetFromTop = - SpillList[i].Offset/4;
280 IfNeededExtSP(MBB, MBBI, dl, TII, MMI, OffsetFromTop, Adjusted, FrameSize,
282 int Offset = Adjusted - OffsetFromTop;
283 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
284 MBB.addLiveIn(SpillList[i].Reg);
285 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
286 .addReg(SpillList[i].Reg, RegState::Kill)
288 .addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
289 MachineMemOperand::MOStore));
290 if (emitFrameMoves) {
291 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
292 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, SpillList[i].Offset);
296 // Complete any remaining Stack adjustment.
297 IfNeededExtSP(MBB, MBBI, dl, TII, MMI, FrameSize, Adjusted, FrameSize,
299 assert(Adjusted==FrameSize && "IfNeededExtSP has not completed adjustment");
302 // Set the FP from the SP.
303 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
305 EmitDefCfaRegister(MBB, MBBI, dl, TII, MMI,
306 MRI->getDwarfRegNum(FramePtr, true));
309 if (emitFrameMoves) {
310 // Frame moves for callee saved.
311 auto SpillLabels = XFI->getSpillLabels();
312 for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
313 MachineBasicBlock::iterator Pos = SpillLabels[I].first;
315 CalleeSavedInfo &CSI = SpillLabels[I].second;
316 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
317 unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
318 EmitCfiOffset(MBB, Pos, dl, TII, MMI, DRegNum, Offset);
320 if (XFI->hasEHSpillSlot()) {
321 // The unwinder requires stack slot & CFI offsets for the exception info.
322 // We do not save/spill these registers.
323 SmallVector<StackSlotInfo,2> SpillList;
324 GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering());
325 assert(SpillList.size()==2 && "Unexpected SpillList size");
326 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
327 MRI->getDwarfRegNum(SpillList[0].Reg, true),
328 SpillList[0].Offset);
329 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
330 MRI->getDwarfRegNum(SpillList[1].Reg, true),
331 SpillList[1].Offset);
336 void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
337 MachineBasicBlock &MBB) const {
338 MachineFrameInfo *MFI = MF.getFrameInfo();
339 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
340 const XCoreInstrInfo &TII =
341 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
342 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
343 DebugLoc dl = MBBI->getDebugLoc();
344 unsigned RetOpcode = MBBI->getOpcode();
346 // Work out frame sizes.
347 // We will adjust the SP in stages towards the final FrameSize.
348 int RemainingAdj = MFI->getStackSize();
349 assert(RemainingAdj%4 == 0 && "Misaligned frame size");
352 if (RetOpcode == XCore::EH_RETURN) {
353 // 'Restore' the exception info the unwinder has placed into the stack
355 SmallVector<StackSlotInfo,2> SpillList;
356 GetEHSpillList(SpillList, MFI, XFI, MF.getTarget().getTargetLowering());
357 RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
359 // Return to the landing pad.
360 unsigned EhStackReg = MBBI->getOperand(0).getReg();
361 unsigned EhHandlerReg = MBBI->getOperand(1).getReg();
362 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
363 BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
364 MBB.erase(MBBI); // Erase the previous return instruction.
368 bool restoreLR = XFI->hasLRSpillSlot();
369 bool UseRETSP = restoreLR && RemainingAdj
370 && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
375 if (FP) // Restore the stack pointer.
376 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
378 // If necessary, restore LR and FP from the stack, as we EXTSP.
379 SmallVector<StackSlotInfo,2> SpillList;
380 GetSpillList(SpillList, MFI, XFI, restoreLR, FP);
381 RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
384 // Complete all but one of the remaining Stack adjustments.
385 IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj);
387 // Fold prologue into return instruction
388 assert(RetOpcode == XCore::RETSP_u6
389 || RetOpcode == XCore::RETSP_lu6);
390 int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
391 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
392 .addImm(RemainingAdj);
393 for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
394 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
395 MBB.erase(MBBI); // Erase the previous return instruction.
397 int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 :
399 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
400 // Don't erase the return instruction.
402 } // else Don't erase the return instruction.
405 bool XCoreFrameLowering::
406 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
407 MachineBasicBlock::iterator MI,
408 const std::vector<CalleeSavedInfo> &CSI,
409 const TargetRegisterInfo *TRI) const {
413 MachineFunction *MF = MBB.getParent();
414 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
415 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
416 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
420 DL = MI->getDebugLoc();
422 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
423 it != CSI.end(); ++it) {
424 unsigned Reg = it->getReg();
425 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
426 "LR & FP are always handled in emitPrologue");
428 // Add the callee-saved register as live-in. It's killed at the spill.
430 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
431 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
432 if (emitFrameMoves) {
435 XFI->getSpillLabels().push_back(std::make_pair(Store, *it));
441 bool XCoreFrameLowering::
442 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
443 MachineBasicBlock::iterator MI,
444 const std::vector<CalleeSavedInfo> &CSI,
445 const TargetRegisterInfo *TRI) const{
446 MachineFunction *MF = MBB.getParent();
447 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
448 bool AtStart = MI == MBB.begin();
449 MachineBasicBlock::iterator BeforeI = MI;
452 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
453 it != CSI.end(); ++it) {
454 unsigned Reg = it->getReg();
455 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
456 "LR & FP are always handled in emitEpilogue");
458 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
459 TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
460 assert(MI != MBB.begin() &&
461 "loadRegFromStackSlot didn't insert any code!");
462 // Insert in reverse order. loadRegFromStackSlot can insert multiple
474 // This function eliminates ADJCALLSTACKDOWN,
475 // ADJCALLSTACKUP pseudo instructions
476 void XCoreFrameLowering::
477 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
478 MachineBasicBlock::iterator I) const {
479 const XCoreInstrInfo &TII =
480 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
481 if (!hasReservedCallFrame(MF)) {
482 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
483 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
484 MachineInstr *Old = I;
485 uint64_t Amount = Old->getOperand(0).getImm();
487 // We need to keep the stack aligned properly. To do this, we round the
488 // amount of space needed for the outgoing arguments up to the next
489 // alignment boundary.
490 unsigned Align = getStackAlignment();
491 Amount = (Amount+Align-1)/Align*Align;
493 assert(Amount%4 == 0);
496 bool isU6 = isImmU6(Amount);
497 if (!isU6 && !isImmU16(Amount)) {
498 // FIX could emit multiple instructions in this case.
500 errs() << "eliminateCallFramePseudoInstr size too big: "
503 llvm_unreachable(nullptr);
507 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
508 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
509 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
512 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
513 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
514 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
518 // Replace the pseudo instruction with a new instruction...
526 void XCoreFrameLowering::
527 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
528 RegScavenger *RS) const {
529 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
531 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
533 if (!LRUsed && !MF.getFunction()->isVarArg() &&
534 MF.getFrameInfo()->estimateStackSize(MF))
535 // If we need to extend the stack it is more efficient to use entsp / retsp.
536 // We force the LR to be saved so these instructions are used.
539 if (MF.getMMI().callsUnwindInit() || MF.getMMI().callsEHReturn()) {
540 // The unwinder expects to find spill slots for the exception info regs R0
541 // & R1. These are used during llvm.eh.return() to 'restore' the exception
542 // info. N.B. we do not spill or restore R0, R1 during normal operation.
543 XFI->createEHSpillSlot(MF);
544 // As we will have a stack, we force the LR to be saved.
549 // We will handle the LR in the prologue/epilogue
550 // and allocate space on the stack ourselves.
551 MF.getRegInfo().setPhysRegUnused(XCore::LR);
552 XFI->createLRSpillSlot(MF);
556 // A callee save register is used to hold the FP.
557 // This needs saving / restoring in the epilogue / prologue.
558 XFI->createFPSpillSlot(MF);
561 void XCoreFrameLowering::
562 processFunctionBeforeFrameFinalized(MachineFunction &MF,
563 RegScavenger *RS) const {
564 assert(RS && "requiresRegisterScavenging failed");
565 MachineFrameInfo *MFI = MF.getFrameInfo();
566 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
567 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
568 // Reserve slots close to SP or frame pointer for Scavenging spills.
569 // When using SP for small frames, we don't need any scratch registers.
570 // When using SP for large frames, we may need 2 scratch registers.
571 // When using FP, for large or small frames, we may need 1 scratch register.
572 if (XFI->isLargeFrame(MF) || hasFP(MF))
573 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
576 if (XFI->isLargeFrame(MF) && !hasFP(MF))
577 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),