1 //===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains XCore frame information that doesn't fit anywhere else
13 //===----------------------------------------------------------------------===//
15 #include "XCoreFrameLowering.h"
17 #include "XCoreInstrInfo.h"
18 #include "XCoreMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Target/TargetOptions.h"
32 // helper functions. FIXME: Eliminate.
33 static inline bool isImmU6(unsigned val) {
34 return val < (1 << 6);
37 static inline bool isImmU16(unsigned val) {
38 return val < (1 << 16);
41 static void loadFromStack(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator I,
43 unsigned DstReg, int Offset, DebugLoc dl,
44 const TargetInstrInfo &TII) {
45 assert(Offset%4 == 0 && "Misaligned stack offset");
47 bool isU6 = isImmU6(Offset);
48 if (!isU6 && !isImmU16(Offset))
49 report_fatal_error("loadFromStack offset too big " + Twine(Offset));
50 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
51 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
56 static void storeToStack(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator I,
58 unsigned SrcReg, int Offset, DebugLoc dl,
59 const TargetInstrInfo &TII) {
60 assert(Offset%4 == 0 && "Misaligned stack offset");
62 bool isU6 = isImmU6(Offset);
63 if (!isU6 && !isImmU16(Offset))
64 report_fatal_error("storeToStack offset too big " + Twine(Offset));
65 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
66 BuildMI(MBB, I, dl, TII.get(Opcode))
72 //===----------------------------------------------------------------------===//
73 // XCoreFrameLowering:
74 //===----------------------------------------------------------------------===//
76 XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
77 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0) {
81 bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
82 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
83 MF.getFrameInfo()->hasVarSizedObjects();
86 void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
87 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
88 MachineBasicBlock::iterator MBBI = MBB.begin();
89 MachineFrameInfo *MFI = MF.getFrameInfo();
90 MachineModuleInfo *MMI = &MF.getMMI();
91 const XCoreInstrInfo &TII =
92 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
93 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
94 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
97 const AttributeSet &PAL = MF.getFunction()->getAttributes();
99 if (PAL.hasAttrSomewhere(Attribute::Nest))
100 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
102 // Work out frame sizes.
103 int FrameSize = MFI->getStackSize();
104 assert(FrameSize%4 == 0 && "Misaligned frame size");
107 bool isU6 = isImmU6(FrameSize);
109 if (!isU6 && !isImmU16(FrameSize)) {
110 // FIXME could emit multiple instructions.
111 report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize));
113 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
115 bool saveLR = XFI->getUsesLR();
116 // Do we need to allocate space on the stack?
119 if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
120 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
121 MBB.addLiveIn(XCore::LR);
124 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
126 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
128 if (emitFrameMoves) {
130 // Show update of SP.
131 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
132 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
136 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
137 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
138 MBB.addLiveIn(XCore::LR);
140 if (emitFrameMoves) {
141 MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
142 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
147 // Save R10 to the stack.
148 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
149 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII);
150 // R10 is live-in. It is killed at the spill.
151 MBB.addLiveIn(XCore::R10);
152 if (emitFrameMoves) {
153 MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
154 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
156 // Set the FP from the SP.
157 unsigned FramePtr = XCore::R10;
158 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
160 if (emitFrameMoves) {
161 // Show FP is now valid.
162 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
163 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
168 void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
169 MachineBasicBlock &MBB) const {
170 MachineFrameInfo *MFI = MF.getFrameInfo();
171 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
172 const XCoreInstrInfo &TII =
173 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
174 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
175 DebugLoc dl = MBBI->getDebugLoc();
179 // Restore the stack pointer.
180 unsigned FramePtr = XCore::R10;
181 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
185 // Work out frame sizes.
186 int FrameSize = MFI->getStackSize();
188 assert(FrameSize%4 == 0 && "Misaligned frame size");
192 bool isU6 = isImmU6(FrameSize);
194 if (!isU6 && !isImmU16(FrameSize)) {
195 // FIXME could emit multiple instructions.
196 report_fatal_error("emitEpilogue Frame size too big: " + Twine(FrameSize));
201 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
202 FPSpillOffset += FrameSize*4;
203 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII);
206 bool restoreLR = XFI->getUsesLR();
208 (FrameSize == 0 || MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0)) {
209 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
210 LRSpillOffset += FrameSize*4;
211 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII);
217 // Fold prologue into return instruction
218 assert(MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
219 assert(MBBI->getOpcode() == XCore::RETSP_u6
220 || MBBI->getOpcode() == XCore::RETSP_lu6);
221 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
222 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
223 for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
224 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
227 int Opcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
228 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
233 bool XCoreFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator MI,
235 const std::vector<CalleeSavedInfo> &CSI,
236 const TargetRegisterInfo *TRI) const {
240 MachineFunction *MF = MBB.getParent();
241 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
243 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
244 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
247 if (MI != MBB.end()) DL = MI->getDebugLoc();
249 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
250 it != CSI.end(); ++it) {
251 // Add the callee-saved register as live-in. It's killed at the spill.
252 MBB.addLiveIn(it->getReg());
254 unsigned Reg = it->getReg();
255 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
256 TII.storeRegToStackSlot(MBB, MI, Reg, true,
257 it->getFrameIdx(), RC, TRI);
258 if (emitFrameMoves) {
259 MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
260 BuildMI(MBB, MI, DL, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLabel);
261 XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it));
267 bool XCoreFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator MI,
269 const std::vector<CalleeSavedInfo> &CSI,
270 const TargetRegisterInfo *TRI) const{
271 MachineFunction *MF = MBB.getParent();
272 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
274 bool AtStart = MI == MBB.begin();
275 MachineBasicBlock::iterator BeforeI = MI;
278 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
279 it != CSI.end(); ++it) {
280 unsigned Reg = it->getReg();
281 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
282 TII.loadRegFromStackSlot(MBB, MI, it->getReg(), it->getFrameIdx(),
284 assert(MI != MBB.begin() &&
285 "loadRegFromStackSlot didn't insert any code!");
286 // Insert in reverse order. loadRegFromStackSlot can insert multiple
298 // This function eliminates ADJCALLSTACKDOWN,
299 // ADJCALLSTACKUP pseudo instructions
300 void XCoreFrameLowering::
301 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
302 MachineBasicBlock::iterator I) const {
303 const XCoreInstrInfo &TII =
304 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
305 if (!hasReservedCallFrame(MF)) {
306 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
307 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
308 MachineInstr *Old = I;
309 uint64_t Amount = Old->getOperand(0).getImm();
311 // We need to keep the stack aligned properly. To do this, we round the
312 // amount of space needed for the outgoing arguments up to the next
313 // alignment boundary.
314 unsigned Align = getStackAlignment();
315 Amount = (Amount+Align-1)/Align*Align;
317 assert(Amount%4 == 0);
320 bool isU6 = isImmU6(Amount);
321 if (!isU6 && !isImmU16(Amount)) {
322 // FIX could emit multiple instructions in this case.
324 errs() << "eliminateCallFramePseudoInstr size too big: "
331 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
332 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
333 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
336 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
337 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
338 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
342 // Replace the pseudo instruction with a new instruction...
351 XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
352 RegScavenger *RS) const {
353 MachineFrameInfo *MFI = MF.getFrameInfo();
354 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
355 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
356 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
357 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
359 MF.getRegInfo().setPhysRegUnused(XCore::LR);
361 bool isVarArg = MF.getFunction()->isVarArg();
364 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
365 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
367 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
370 XFI->setUsesLR(FrameIdx);
371 XFI->setLRSpillSlot(FrameIdx);
373 if (RegInfo->requiresRegisterScavenging(MF)) {
374 // Reserve a slot close to SP or frame pointer.
375 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
380 // A callee save register is used to hold the FP.
381 // This needs saving / restoring in the epilogue / prologue.
382 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),