1 //===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the XCore target.
12 //===----------------------------------------------------------------------===//
15 #include "XCoreTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
37 /// XCoreDAGToDAGISel - XCore specific code to select XCore machine
38 /// instructions for SelectionDAG operations.
41 class XCoreDAGToDAGISel : public SelectionDAGISel {
42 const XCoreTargetLowering &Lowering;
43 const XCoreSubtarget &Subtarget;
46 XCoreDAGToDAGISel(XCoreTargetMachine &TM)
47 : SelectionDAGISel(TM),
48 Lowering(*TM.getTargetLowering()),
49 Subtarget(*TM.getSubtargetImpl()) { }
51 SDNode *Select(SDNode *N);
53 /// getI32Imm - Return a target constant with the specified value, of type
55 inline SDValue getI32Imm(unsigned Imm) {
56 return CurDAG->getTargetConstant(Imm, MVT::i32);
59 inline bool immMskBitp(SDNode *inN) const {
60 ConstantSDNode *N = cast<ConstantSDNode>(inN);
61 uint32_t value = (uint32_t)N->getZExtValue();
62 if (!isMask_32(value)) {
65 int msksize = 32 - CountLeadingZeros_32(value);
66 return (msksize >= 1 && msksize <= 8) ||
67 msksize == 16 || msksize == 24 || msksize == 32;
70 // Complex Pattern Selectors.
71 bool SelectADDRspii(SDNode *Op, SDValue Addr, SDValue &Base,
73 bool SelectADDRdpii(SDNode *Op, SDValue Addr, SDValue &Base,
75 bool SelectADDRcpii(SDNode *Op, SDValue Addr, SDValue &Base,
78 virtual const char *getPassName() const {
79 return "XCore DAG->DAG Pattern Instruction Selection";
82 // Include the pieces autogenerated from the target description.
83 #include "XCoreGenDAGISel.inc"
85 } // end anonymous namespace
87 /// createXCoreISelDag - This pass converts a legalized DAG into a
88 /// XCore-specific DAG, ready for instruction scheduling.
90 FunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM) {
91 return new XCoreDAGToDAGISel(TM);
94 bool XCoreDAGToDAGISel::SelectADDRspii(SDNode *Op, SDValue Addr,
95 SDValue &Base, SDValue &Offset) {
96 FrameIndexSDNode *FIN = 0;
97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
98 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
99 Offset = CurDAG->getTargetConstant(0, MVT::i32);
102 if (Addr.getOpcode() == ISD::ADD) {
103 ConstantSDNode *CN = 0;
104 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
105 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
106 && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
107 // Constant positive word offset from frame index
108 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
109 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
116 bool XCoreDAGToDAGISel::SelectADDRdpii(SDNode *Op, SDValue Addr,
117 SDValue &Base, SDValue &Offset) {
118 if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
119 Base = Addr.getOperand(0);
120 Offset = CurDAG->getTargetConstant(0, MVT::i32);
123 if (Addr.getOpcode() == ISD::ADD) {
124 ConstantSDNode *CN = 0;
125 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
126 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
127 && (CN->getSExtValue() % 4 == 0)) {
128 // Constant word offset from a object in the data region
129 Base = Addr.getOperand(0).getOperand(0);
130 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
137 bool XCoreDAGToDAGISel::SelectADDRcpii(SDNode *Op, SDValue Addr,
138 SDValue &Base, SDValue &Offset) {
139 if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
140 Base = Addr.getOperand(0);
141 Offset = CurDAG->getTargetConstant(0, MVT::i32);
144 if (Addr.getOpcode() == ISD::ADD) {
145 ConstantSDNode *CN = 0;
146 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
147 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
148 && (CN->getSExtValue() % 4 == 0)) {
149 // Constant word offset from a object in the data region
150 Base = Addr.getOperand(0).getOperand(0);
151 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
158 SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
159 DebugLoc dl = N->getDebugLoc();
160 EVT NVT = N->getValueType(0);
161 if (NVT == MVT::i32) {
162 switch (N->getOpcode()) {
164 case ISD::Constant: {
165 uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
167 // Transformation function: get the size of a mask
168 // Look for the first non-zero bit
169 SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val));
170 return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,
173 else if (!isUInt<16>(Val)) {
175 CurDAG->getTargetConstantPool(ConstantInt::get(
176 Type::getInt32Ty(*CurDAG->getContext()), Val),
178 return CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32,
180 CurDAG->getEntryNode());
184 case XCoreISD::LADD: {
185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
187 return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
190 case XCoreISD::LSUB: {
191 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
193 return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
196 case XCoreISD::MACCU: {
197 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
198 N->getOperand(2), N->getOperand(3) };
199 return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32,
202 case XCoreISD::MACCS: {
203 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
204 N->getOperand(2), N->getOperand(3) };
205 return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
208 case XCoreISD::LMUL: {
209 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
210 N->getOperand(2), N->getOperand(3) };
211 return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
214 // Other cases are autogenerated.
217 return SelectCode(N);