1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the XCoreTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "xcore-lower"
16 #include "XCoreISelLowering.h"
17 #include "XCoreMachineFunctionInfo.h"
19 #include "XCoreTargetObjectFile.h"
20 #include "XCoreTargetMachine.h"
21 #include "XCoreSubtarget.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/GlobalAlias.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAGISel.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
41 const char *XCoreTargetLowering::
42 getTargetNodeName(unsigned Opcode) const
46 case XCoreISD::BL : return "XCoreISD::BL";
47 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
48 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
49 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
50 case XCoreISD::STWSP : return "XCoreISD::STWSP";
51 case XCoreISD::RETSP : return "XCoreISD::RETSP";
52 case XCoreISD::LADD : return "XCoreISD::LADD";
53 case XCoreISD::LSUB : return "XCoreISD::LSUB";
54 case XCoreISD::LMUL : return "XCoreISD::LMUL";
55 case XCoreISD::MACCU : return "XCoreISD::MACCU";
56 case XCoreISD::MACCS : return "XCoreISD::MACCS";
57 case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
58 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
59 default : return NULL;
63 XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
64 : TargetLowering(XTM, new XCoreTargetObjectFile()),
66 Subtarget(*XTM.getSubtargetImpl()) {
68 // Set up the register classes.
69 addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
71 // Compute derived properties from the register classes
72 computeRegisterProperties();
74 // Division is expensive
75 setIntDivIsCheap(false);
77 setStackPointerRegisterToSaveRestore(XCore::SP);
79 setSchedulingPreference(Sched::RegPressure);
81 // Use i32 for setcc operations results (slt, sgt, ...).
82 setBooleanContents(ZeroOrOneBooleanContent);
83 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
85 // XCore does not have the NodeTypes below.
86 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
87 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
88 setOperationAction(ISD::ADDC, MVT::i32, Expand);
89 setOperationAction(ISD::ADDE, MVT::i32, Expand);
90 setOperationAction(ISD::SUBC, MVT::i32, Expand);
91 setOperationAction(ISD::SUBE, MVT::i32, Expand);
93 // Stop the combiner recombining select and set_cc
94 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
97 setOperationAction(ISD::ADD, MVT::i64, Custom);
98 setOperationAction(ISD::SUB, MVT::i64, Custom);
99 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
100 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
101 setOperationAction(ISD::MULHS, MVT::i32, Expand);
102 setOperationAction(ISD::MULHU, MVT::i32, Expand);
103 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
104 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
105 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
108 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
109 setOperationAction(ISD::ROTL , MVT::i32, Expand);
110 setOperationAction(ISD::ROTR , MVT::i32, Expand);
111 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
112 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
114 setOperationAction(ISD::TRAP, MVT::Other, Legal);
117 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
119 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
120 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
122 // Thread Local Storage
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
125 // Conversion of i64 -> double produces constantpool nodes
126 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
133 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
134 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
136 // Custom expand misaligned loads / stores.
137 setOperationAction(ISD::LOAD, MVT::i32, Custom);
138 setOperationAction(ISD::STORE, MVT::i32, Custom);
141 setOperationAction(ISD::VAEND, MVT::Other, Expand);
142 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
143 setOperationAction(ISD::VAARG, MVT::Other, Custom);
144 setOperationAction(ISD::VASTART, MVT::Other, Custom);
147 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
148 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
149 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
151 // TRAMPOLINE is custom lowered.
152 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
153 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
155 maxStoresPerMemset = maxStoresPerMemsetOptSize = 4;
156 maxStoresPerMemmove = maxStoresPerMemmoveOptSize
157 = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2;
159 // We have target-specific dag combine patterns for the following nodes:
160 setTargetDAGCombine(ISD::STORE);
161 setTargetDAGCombine(ISD::ADD);
163 setMinFunctionAlignment(1);
166 SDValue XCoreTargetLowering::
167 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
168 switch (Op.getOpcode())
170 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
171 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
172 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
173 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
174 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
175 case ISD::LOAD: return LowerLOAD(Op, DAG);
176 case ISD::STORE: return LowerSTORE(Op, DAG);
177 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
178 case ISD::VAARG: return LowerVAARG(Op, DAG);
179 case ISD::VASTART: return LowerVASTART(Op, DAG);
180 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
181 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
182 // FIXME: Remove these when LegalizeDAGTypes lands.
184 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
185 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
186 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
187 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
189 llvm_unreachable("unimplemented operand");
193 /// ReplaceNodeResults - Replace the results of node with an illegal result
194 /// type with new values built out of custom code.
195 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
196 SmallVectorImpl<SDValue>&Results,
197 SelectionDAG &DAG) const {
198 switch (N->getOpcode()) {
200 llvm_unreachable("Don't know how to custom expand this!");
203 Results.push_back(ExpandADDSUB(N, DAG));
208 //===----------------------------------------------------------------------===//
209 // Misc Lower Operation implementation
210 //===----------------------------------------------------------------------===//
212 SDValue XCoreTargetLowering::
213 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
215 DebugLoc dl = Op.getDebugLoc();
216 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
217 Op.getOperand(3), Op.getOperand(4));
218 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
222 SDValue XCoreTargetLowering::
223 getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
224 SelectionDAG &DAG) const
226 // FIXME there is no actual debug info here
227 DebugLoc dl = GA.getDebugLoc();
228 if (isa<Function>(GV)) {
229 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
231 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
233 // If GV is an alias then use the aliasee to determine constness
234 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
235 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
237 bool isConst = GVar && GVar->isConstant();
239 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
241 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
244 SDValue XCoreTargetLowering::
245 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
247 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
248 SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), MVT::i32);
249 return getGlobalAddressWrapper(GA, GV, DAG);
252 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
253 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
254 DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
257 static inline bool isZeroLengthArray(Type *Ty) {
258 ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty);
259 return AT && (AT->getNumElements() == 0);
262 SDValue XCoreTargetLowering::
263 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
265 // FIXME there isn't really debug info here
266 DebugLoc dl = Op.getDebugLoc();
267 // transform to label + getid() * size
268 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
269 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
270 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
272 // If GV is an alias then use the aliasee to determine size
273 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
274 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
277 llvm_unreachable("Thread local object not a GlobalVariable?");
279 Type *Ty = cast<PointerType>(GV->getType())->getElementType();
280 if (!Ty->isSized() || isZeroLengthArray(Ty)) {
282 errs() << "Size of thread local object " << GVar->getName()
287 SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
288 const TargetData *TD = TM.getTargetData();
289 unsigned Size = TD->getTypeAllocSize(Ty);
290 SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
291 DAG.getConstant(Size, MVT::i32));
292 return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
295 SDValue XCoreTargetLowering::
296 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
298 DebugLoc DL = Op.getDebugLoc();
300 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
301 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
303 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
306 SDValue XCoreTargetLowering::
307 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
309 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
310 // FIXME there isn't really debug info here
311 DebugLoc dl = CP->getDebugLoc();
312 EVT PtrVT = Op.getValueType();
314 if (CP->isMachineConstantPoolEntry()) {
315 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
318 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
321 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
324 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
325 return MachineJumpTableInfo::EK_Inline;
328 SDValue XCoreTargetLowering::
329 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
331 SDValue Chain = Op.getOperand(0);
332 SDValue Table = Op.getOperand(1);
333 SDValue Index = Op.getOperand(2);
334 DebugLoc dl = Op.getDebugLoc();
335 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
336 unsigned JTI = JT->getIndex();
337 MachineFunction &MF = DAG.getMachineFunction();
338 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
339 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
341 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
342 if (NumEntries <= 32) {
343 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
345 assert((NumEntries >> 31) == 0);
346 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
347 DAG.getConstant(1, MVT::i32));
348 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
353 IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase,
356 if (Addr.getOpcode() != ISD::ADD) {
359 ConstantSDNode *CN = 0;
360 if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
363 int64_t off = CN->getSExtValue();
364 const SDValue &Base = Addr.getOperand(0);
365 const SDValue *Root = &Base;
366 if (Base.getOpcode() == ISD::ADD &&
367 Base.getOperand(1).getOpcode() == ISD::SHL) {
368 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1)
370 if (CN && (CN->getSExtValue() >= 2)) {
371 Root = &Base.getOperand(0);
374 if (isa<FrameIndexSDNode>(*Root)) {
375 // All frame indicies are word aligned
380 if (Root->getOpcode() == XCoreISD::DPRelativeWrapper ||
381 Root->getOpcode() == XCoreISD::CPRelativeWrapper) {
382 // All dp / cp relative addresses are word aligned
387 // Check for an aligned global variable.
388 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) {
389 const GlobalValue *GV = GA->getGlobal();
390 if (GA->getOffset() == 0 && GV->getAlignment() >= 4) {
399 SDValue XCoreTargetLowering::
400 LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
401 LoadSDNode *LD = cast<LoadSDNode>(Op);
402 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
403 "Unexpected extension type");
404 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
405 if (allowsUnalignedMemoryAccesses(LD->getMemoryVT()))
408 unsigned ABIAlignment = getTargetData()->
409 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
410 // Leave aligned load alone.
411 if (LD->getAlignment() >= ABIAlignment)
414 SDValue Chain = LD->getChain();
415 SDValue BasePtr = LD->getBasePtr();
416 DebugLoc DL = Op.getDebugLoc();
420 if (!LD->isVolatile() &&
421 IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) {
422 if (Offset % 4 == 0) {
423 // We've managed to infer better alignment information than the load
424 // already has. Use an aligned load.
426 return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
427 MachinePointerInfo(),
428 false, false, false, 0);
431 // ldw low, base[offset >> 2]
432 // ldw high, base[(offset >> 2) + 1]
433 // shr low_shifted, low, (offset & 0x3) * 8
434 // shl high_shifted, high, 32 - (offset & 0x3) * 8
435 // or result, low_shifted, high_shifted
436 SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32);
437 SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32);
438 SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
439 SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
441 SDValue LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowOffset);
442 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset);
444 SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
445 LowAddr, MachinePointerInfo(),
446 false, false, false, 0);
447 SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
448 HighAddr, MachinePointerInfo(),
449 false, false, false, 0);
450 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
451 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
452 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
453 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
455 SDValue Ops[] = { Result, Chain };
456 return DAG.getMergeValues(Ops, 2, DL);
459 if (LD->getAlignment() == 2) {
460 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
461 BasePtr, LD->getPointerInfo(), MVT::i16,
462 LD->isVolatile(), LD->isNonTemporal(), 2);
463 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
464 DAG.getConstant(2, MVT::i32));
465 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
467 LD->getPointerInfo().getWithOffset(2),
468 MVT::i16, LD->isVolatile(),
469 LD->isNonTemporal(), 2);
470 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
471 DAG.getConstant(16, MVT::i32));
472 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
473 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
475 SDValue Ops[] = { Result, Chain };
476 return DAG.getMergeValues(Ops, 2, DL);
479 // Lower to a call to __misaligned_load(BasePtr).
480 Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
481 TargetLowering::ArgListTy Args;
482 TargetLowering::ArgListEntry Entry;
485 Entry.Node = BasePtr;
486 Args.push_back(Entry);
488 std::pair<SDValue, SDValue> CallResult =
489 LowerCallTo(Chain, IntPtrTy, false, false,
490 false, false, 0, CallingConv::C, /*isTailCall=*/false,
491 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
492 DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
496 { CallResult.first, CallResult.second };
498 return DAG.getMergeValues(Ops, 2, DL);
501 SDValue XCoreTargetLowering::
502 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
504 StoreSDNode *ST = cast<StoreSDNode>(Op);
505 assert(!ST->isTruncatingStore() && "Unexpected store type");
506 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
507 if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
510 unsigned ABIAlignment = getTargetData()->
511 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
512 // Leave aligned store alone.
513 if (ST->getAlignment() >= ABIAlignment) {
516 SDValue Chain = ST->getChain();
517 SDValue BasePtr = ST->getBasePtr();
518 SDValue Value = ST->getValue();
519 DebugLoc dl = Op.getDebugLoc();
521 if (ST->getAlignment() == 2) {
523 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
524 DAG.getConstant(16, MVT::i32));
525 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
526 ST->getPointerInfo(), MVT::i16,
527 ST->isVolatile(), ST->isNonTemporal(),
529 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
530 DAG.getConstant(2, MVT::i32));
531 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
532 ST->getPointerInfo().getWithOffset(2),
533 MVT::i16, ST->isVolatile(),
534 ST->isNonTemporal(), 2);
535 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
538 // Lower to a call to __misaligned_store(BasePtr, Value).
539 Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
540 TargetLowering::ArgListTy Args;
541 TargetLowering::ArgListEntry Entry;
544 Entry.Node = BasePtr;
545 Args.push_back(Entry);
548 Args.push_back(Entry);
550 std::pair<SDValue, SDValue> CallResult =
551 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false,
552 false, false, 0, CallingConv::C, /*isTailCall=*/false,
553 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
554 DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
557 return CallResult.second;
560 SDValue XCoreTargetLowering::
561 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
563 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
564 "Unexpected operand to lower!");
565 DebugLoc dl = Op.getDebugLoc();
566 SDValue LHS = Op.getOperand(0);
567 SDValue RHS = Op.getOperand(1);
568 SDValue Zero = DAG.getConstant(0, MVT::i32);
569 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
570 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
572 SDValue Lo(Hi.getNode(), 1);
573 SDValue Ops[] = { Lo, Hi };
574 return DAG.getMergeValues(Ops, 2, dl);
577 SDValue XCoreTargetLowering::
578 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
580 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
581 "Unexpected operand to lower!");
582 DebugLoc dl = Op.getDebugLoc();
583 SDValue LHS = Op.getOperand(0);
584 SDValue RHS = Op.getOperand(1);
585 SDValue Zero = DAG.getConstant(0, MVT::i32);
586 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
587 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
589 SDValue Lo(Hi.getNode(), 1);
590 SDValue Ops[] = { Lo, Hi };
591 return DAG.getMergeValues(Ops, 2, dl);
594 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
595 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
596 /// each intermediate result in the calculation must also have a single use.
597 /// If the Op is in the correct form the constituent parts are written to Mul0,
598 /// Mul1, Addend0 and Addend1.
600 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
601 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
603 if (Op.getOpcode() != ISD::ADD)
605 SDValue N0 = Op.getOperand(0);
606 SDValue N1 = Op.getOperand(1);
609 if (N0.getOpcode() == ISD::ADD) {
612 } else if (N1.getOpcode() == ISD::ADD) {
618 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
620 if (OtherOp.getOpcode() == ISD::MUL) {
621 // add(add(a,b),mul(x,y))
622 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
624 Mul0 = OtherOp.getOperand(0);
625 Mul1 = OtherOp.getOperand(1);
626 Addend0 = AddOp.getOperand(0);
627 Addend1 = AddOp.getOperand(1);
630 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
631 // add(add(mul(x,y),a),b)
632 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
634 Mul0 = AddOp.getOperand(0).getOperand(0);
635 Mul1 = AddOp.getOperand(0).getOperand(1);
636 Addend0 = AddOp.getOperand(1);
640 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
641 // add(add(a,mul(x,y)),b)
642 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
644 Mul0 = AddOp.getOperand(1).getOperand(0);
645 Mul1 = AddOp.getOperand(1).getOperand(1);
646 Addend0 = AddOp.getOperand(0);
653 SDValue XCoreTargetLowering::
654 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
658 if (N->getOperand(0).getOpcode() == ISD::MUL) {
659 Mul = N->getOperand(0);
660 Other = N->getOperand(1);
661 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
662 Mul = N->getOperand(1);
663 Other = N->getOperand(0);
667 DebugLoc dl = N->getDebugLoc();
668 SDValue LL, RL, AddendL, AddendH;
669 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
670 Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
671 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
672 Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
673 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
674 Other, DAG.getConstant(0, MVT::i32));
675 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
676 Other, DAG.getConstant(1, MVT::i32));
677 APInt HighMask = APInt::getHighBitsSet(64, 32);
678 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
679 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
680 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
681 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
682 // The inputs are both zero-extended.
683 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
684 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
686 SDValue Lo(Hi.getNode(), 1);
687 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
689 if (LHSSB > 32 && RHSSB > 32) {
690 // The inputs are both sign-extended.
691 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
692 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
694 SDValue Lo(Hi.getNode(), 1);
695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
698 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
699 Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
700 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
701 Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
702 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
703 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
705 SDValue Lo(Hi.getNode(), 1);
706 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
707 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
708 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
709 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
710 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
713 SDValue XCoreTargetLowering::
714 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
716 assert(N->getValueType(0) == MVT::i64 &&
717 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
718 "Unknown operand to lower!");
720 if (N->getOpcode() == ISD::ADD) {
721 SDValue Result = TryExpandADDWithMul(N, DAG);
722 if (Result.getNode() != 0)
726 DebugLoc dl = N->getDebugLoc();
728 // Extract components
729 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
730 N->getOperand(0), DAG.getConstant(0, MVT::i32));
731 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
732 N->getOperand(0), DAG.getConstant(1, MVT::i32));
733 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
734 N->getOperand(1), DAG.getConstant(0, MVT::i32));
735 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
736 N->getOperand(1), DAG.getConstant(1, MVT::i32));
739 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
741 SDValue Zero = DAG.getConstant(0, MVT::i32);
742 SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
744 SDValue Lo(Carry.getNode(), 1);
746 SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
748 SDValue Hi(Ignored.getNode(), 1);
750 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
753 SDValue XCoreTargetLowering::
754 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
756 llvm_unreachable("unimplemented");
757 // FIXME Arguments passed by reference need a extra dereference.
758 SDNode *Node = Op.getNode();
759 DebugLoc dl = Node->getDebugLoc();
760 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
761 EVT VT = Node->getValueType(0);
762 SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
763 Node->getOperand(1), MachinePointerInfo(V),
764 false, false, false, 0);
765 // Increment the pointer, VAList, to the next vararg
766 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
767 DAG.getConstant(VT.getSizeInBits(),
769 // Store the incremented VAList to the legalized pointer
770 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1),
771 MachinePointerInfo(V), false, false, 0);
772 // Load the actual argument out of the pointer VAList
773 return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
774 false, false, false, 0);
777 SDValue XCoreTargetLowering::
778 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
780 DebugLoc dl = Op.getDebugLoc();
781 // vastart stores the address of the VarArgsFrameIndex slot into the
782 // memory location argument
783 MachineFunction &MF = DAG.getMachineFunction();
784 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
785 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
786 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
787 MachinePointerInfo(), false, false, 0);
790 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
791 SelectionDAG &DAG) const {
792 DebugLoc dl = Op.getDebugLoc();
793 // Depths > 0 not supported yet!
794 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
797 MachineFunction &MF = DAG.getMachineFunction();
798 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
799 return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
800 RegInfo->getFrameRegister(MF), MVT::i32);
803 SDValue XCoreTargetLowering::
804 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
805 return Op.getOperand(0);
808 SDValue XCoreTargetLowering::
809 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
810 SDValue Chain = Op.getOperand(0);
811 SDValue Trmp = Op.getOperand(1); // trampoline
812 SDValue FPtr = Op.getOperand(2); // nested function
813 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
815 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
818 // LDAPF_u10 r11, nest
819 // LDW_2rus r11, r11[0]
820 // STWSP_ru6 r11, sp[0]
821 // LDAPF_u10 r11, fptr
822 // LDW_2rus r11, r11[0]
828 SDValue OutChains[5];
832 DebugLoc dl = Op.getDebugLoc();
833 OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
834 Addr, MachinePointerInfo(TrmpAddr), false, false,
837 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
838 DAG.getConstant(4, MVT::i32));
839 OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
840 Addr, MachinePointerInfo(TrmpAddr, 4), false,
843 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
844 DAG.getConstant(8, MVT::i32));
845 OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
846 Addr, MachinePointerInfo(TrmpAddr, 8), false,
849 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
850 DAG.getConstant(12, MVT::i32));
851 OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
852 MachinePointerInfo(TrmpAddr, 12), false, false,
855 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
856 DAG.getConstant(16, MVT::i32));
857 OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
858 MachinePointerInfo(TrmpAddr, 16), false, false,
861 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5);
864 //===----------------------------------------------------------------------===//
865 // Calling Convention Implementation
866 //===----------------------------------------------------------------------===//
868 #include "XCoreGenCallingConv.inc"
870 //===----------------------------------------------------------------------===//
871 // Call Calling Convention Implementation
872 //===----------------------------------------------------------------------===//
874 /// XCore call implementation
876 XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
877 CallingConv::ID CallConv, bool isVarArg,
878 bool doesNotRet, bool &isTailCall,
879 const SmallVectorImpl<ISD::OutputArg> &Outs,
880 const SmallVectorImpl<SDValue> &OutVals,
881 const SmallVectorImpl<ISD::InputArg> &Ins,
882 DebugLoc dl, SelectionDAG &DAG,
883 SmallVectorImpl<SDValue> &InVals) const {
884 // XCore target does not yet support tail call optimization.
887 // For now, only CallingConv::C implemented
891 llvm_unreachable("Unsupported calling convention");
892 case CallingConv::Fast:
894 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
895 Outs, OutVals, Ins, dl, DAG, InVals);
899 /// LowerCCCCallTo - functions arguments are copied from virtual
900 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
901 /// CALLSEQ_END are emitted.
902 /// TODO: isTailCall, sret.
904 XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
905 CallingConv::ID CallConv, bool isVarArg,
907 const SmallVectorImpl<ISD::OutputArg> &Outs,
908 const SmallVectorImpl<SDValue> &OutVals,
909 const SmallVectorImpl<ISD::InputArg> &Ins,
910 DebugLoc dl, SelectionDAG &DAG,
911 SmallVectorImpl<SDValue> &InVals) const {
913 // Analyze operands of the call, assigning locations to each operand.
914 SmallVector<CCValAssign, 16> ArgLocs;
915 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
916 getTargetMachine(), ArgLocs, *DAG.getContext());
918 // The ABI dictates there should be one stack slot available to the callee
919 // on function entry (for saving lr).
920 CCInfo.AllocateStack(4, 4);
922 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
924 // Get a count of how many bytes are to be pushed on the stack.
925 unsigned NumBytes = CCInfo.getNextStackOffset();
927 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
928 getPointerTy(), true));
930 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
931 SmallVector<SDValue, 12> MemOpChains;
933 // Walk the register/memloc assignments, inserting copies/loads.
934 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
935 CCValAssign &VA = ArgLocs[i];
936 SDValue Arg = OutVals[i];
938 // Promote the value if needed.
939 switch (VA.getLocInfo()) {
940 default: llvm_unreachable("Unknown loc info!");
941 case CCValAssign::Full: break;
942 case CCValAssign::SExt:
943 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
945 case CCValAssign::ZExt:
946 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
948 case CCValAssign::AExt:
949 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
953 // Arguments that can be passed on register must be kept at
956 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
958 assert(VA.isMemLoc());
960 int Offset = VA.getLocMemOffset();
962 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
964 DAG.getConstant(Offset/4, MVT::i32)));
968 // Transform all store nodes into one single node because
969 // all store nodes are independent of each other.
970 if (!MemOpChains.empty())
971 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
972 &MemOpChains[0], MemOpChains.size());
974 // Build a sequence of copy-to-reg nodes chained together with token
975 // chain and flag operands which copy the outgoing args into registers.
976 // The InFlag in necessary since all emitted instructions must be
979 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
980 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
981 RegsToPass[i].second, InFlag);
982 InFlag = Chain.getValue(1);
985 // If the callee is a GlobalAddress node (quite common, every direct call is)
986 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
987 // Likewise ExternalSymbol -> TargetExternalSymbol.
988 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
989 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
990 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
991 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
993 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
994 // = Chain, Callee, Reg#1, Reg#2, ...
996 // Returns a chain & a flag for retval copy to use.
997 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
998 SmallVector<SDValue, 8> Ops;
999 Ops.push_back(Chain);
1000 Ops.push_back(Callee);
1002 // Add argument registers to the end of the list so that they are
1003 // known live into the call.
1004 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1005 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1006 RegsToPass[i].second.getValueType()));
1008 if (InFlag.getNode())
1009 Ops.push_back(InFlag);
1011 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
1012 InFlag = Chain.getValue(1);
1014 // Create the CALLSEQ_END node.
1015 Chain = DAG.getCALLSEQ_END(Chain,
1016 DAG.getConstant(NumBytes, getPointerTy(), true),
1017 DAG.getConstant(0, getPointerTy(), true),
1019 InFlag = Chain.getValue(1);
1021 // Handle result values, copying them out of physregs into vregs that we
1023 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1024 Ins, dl, DAG, InVals);
1027 /// LowerCallResult - Lower the result values of a call into the
1028 /// appropriate copies out of appropriate physical registers.
1030 XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1031 CallingConv::ID CallConv, bool isVarArg,
1032 const SmallVectorImpl<ISD::InputArg> &Ins,
1033 DebugLoc dl, SelectionDAG &DAG,
1034 SmallVectorImpl<SDValue> &InVals) const {
1036 // Assign locations to each value returned by this call.
1037 SmallVector<CCValAssign, 16> RVLocs;
1038 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1039 getTargetMachine(), RVLocs, *DAG.getContext());
1041 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1043 // Copy all of the result registers out of their specified physreg.
1044 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1045 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1046 RVLocs[i].getValVT(), InFlag).getValue(1);
1047 InFlag = Chain.getValue(2);
1048 InVals.push_back(Chain.getValue(0));
1054 //===----------------------------------------------------------------------===//
1055 // Formal Arguments Calling Convention Implementation
1056 //===----------------------------------------------------------------------===//
1058 /// XCore formal arguments implementation
1060 XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
1061 CallingConv::ID CallConv,
1063 const SmallVectorImpl<ISD::InputArg> &Ins,
1066 SmallVectorImpl<SDValue> &InVals)
1071 llvm_unreachable("Unsupported calling convention");
1072 case CallingConv::C:
1073 case CallingConv::Fast:
1074 return LowerCCCArguments(Chain, CallConv, isVarArg,
1075 Ins, dl, DAG, InVals);
1079 /// LowerCCCArguments - transform physical registers into
1080 /// virtual registers and generate load operations for
1081 /// arguments places on the stack.
1084 XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
1085 CallingConv::ID CallConv,
1087 const SmallVectorImpl<ISD::InputArg>
1091 SmallVectorImpl<SDValue> &InVals) const {
1092 MachineFunction &MF = DAG.getMachineFunction();
1093 MachineFrameInfo *MFI = MF.getFrameInfo();
1094 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1096 // Assign locations to all of the incoming arguments.
1097 SmallVector<CCValAssign, 16> ArgLocs;
1098 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1099 getTargetMachine(), ArgLocs, *DAG.getContext());
1101 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1103 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1105 unsigned LRSaveSize = StackSlotSize;
1107 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1109 CCValAssign &VA = ArgLocs[i];
1111 if (VA.isRegLoc()) {
1112 // Arguments passed in registers
1113 EVT RegVT = VA.getLocVT();
1114 switch (RegVT.getSimpleVT().SimpleTy) {
1118 errs() << "LowerFormalArguments Unhandled argument type: "
1119 << RegVT.getSimpleVT().SimpleTy << "\n";
1121 llvm_unreachable(0);
1124 unsigned VReg = RegInfo.createVirtualRegister(
1125 XCore::GRRegsRegisterClass);
1126 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1127 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1131 assert(VA.isMemLoc());
1132 // Load the argument to a virtual register
1133 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1134 if (ObjSize > StackSlotSize) {
1135 errs() << "LowerFormalArguments Unhandled argument type: "
1136 << EVT(VA.getLocVT()).getEVTString()
1139 // Create the frame index object for this incoming parameter...
1140 int FI = MFI->CreateFixedObject(ObjSize,
1141 LRSaveSize + VA.getLocMemOffset(),
1144 // Create the SelectionDAG nodes corresponding to a load
1145 //from this parameter
1146 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1147 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1148 MachinePointerInfo::getFixedStack(FI),
1149 false, false, false, 0));
1154 /* Argument registers */
1155 static const uint16_t ArgRegs[] = {
1156 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1158 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1159 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
1160 array_lengthof(ArgRegs));
1161 if (FirstVAReg < array_lengthof(ArgRegs)) {
1162 SmallVector<SDValue, 4> MemOps;
1164 // Save remaining registers, storing higher register numbers at a higher
1166 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1167 // Create a stack slot
1168 int FI = MFI->CreateFixedObject(4, offset, true);
1169 if (i == (int)FirstVAReg) {
1170 XFI->setVarArgsFrameIndex(FI);
1172 offset -= StackSlotSize;
1173 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1174 // Move argument from phys reg -> virt reg
1175 unsigned VReg = RegInfo.createVirtualRegister(
1176 XCore::GRRegsRegisterClass);
1177 RegInfo.addLiveIn(ArgRegs[i], VReg);
1178 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1179 // Move argument from virt reg -> stack
1180 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1181 MachinePointerInfo(), false, false, 0);
1182 MemOps.push_back(Store);
1184 if (!MemOps.empty())
1185 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1186 &MemOps[0], MemOps.size());
1188 // This will point to the next argument passed via stack.
1189 XFI->setVarArgsFrameIndex(
1190 MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1198 //===----------------------------------------------------------------------===//
1199 // Return Value Calling Convention Implementation
1200 //===----------------------------------------------------------------------===//
1202 bool XCoreTargetLowering::
1203 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1205 const SmallVectorImpl<ISD::OutputArg> &Outs,
1206 LLVMContext &Context) const {
1207 SmallVector<CCValAssign, 16> RVLocs;
1208 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
1209 return CCInfo.CheckReturn(Outs, RetCC_XCore);
1213 XCoreTargetLowering::LowerReturn(SDValue Chain,
1214 CallingConv::ID CallConv, bool isVarArg,
1215 const SmallVectorImpl<ISD::OutputArg> &Outs,
1216 const SmallVectorImpl<SDValue> &OutVals,
1217 DebugLoc dl, SelectionDAG &DAG) const {
1219 // CCValAssign - represent the assignment of
1220 // the return value to a location
1221 SmallVector<CCValAssign, 16> RVLocs;
1223 // CCState - Info about the registers and stack slot.
1224 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1225 getTargetMachine(), RVLocs, *DAG.getContext());
1227 // Analyze return values.
1228 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1230 // If this is the first return lowered for this function, add
1231 // the regs to the liveout set for the function.
1232 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1233 for (unsigned i = 0; i != RVLocs.size(); ++i)
1234 if (RVLocs[i].isRegLoc())
1235 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1240 // Copy the result values into the output registers.
1241 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1242 CCValAssign &VA = RVLocs[i];
1243 assert(VA.isRegLoc() && "Can only return in registers!");
1245 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1248 // guarantee that all emitted copies are
1249 // stuck together, avoiding something bad
1250 Flag = Chain.getValue(1);
1253 // Return on XCore is always a "retsp 0"
1255 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1256 Chain, DAG.getConstant(0, MVT::i32), Flag);
1258 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1259 Chain, DAG.getConstant(0, MVT::i32));
1262 //===----------------------------------------------------------------------===//
1263 // Other Lowering Code
1264 //===----------------------------------------------------------------------===//
1267 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1268 MachineBasicBlock *BB) const {
1269 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1270 DebugLoc dl = MI->getDebugLoc();
1271 assert((MI->getOpcode() == XCore::SELECT_CC) &&
1272 "Unexpected instr type to insert");
1274 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1275 // control-flow pattern. The incoming instruction knows the destination vreg
1276 // to set, the condition code register to branch on, the true/false values to
1277 // select between, and a branch opcode to use.
1278 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1279 MachineFunction::iterator It = BB;
1285 // cmpTY ccX, r1, r2
1287 // fallthrough --> copy0MBB
1288 MachineBasicBlock *thisMBB = BB;
1289 MachineFunction *F = BB->getParent();
1290 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1291 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1292 F->insert(It, copy0MBB);
1293 F->insert(It, sinkMBB);
1295 // Transfer the remainder of BB and its successor edges to sinkMBB.
1296 sinkMBB->splice(sinkMBB->begin(), BB,
1297 llvm::next(MachineBasicBlock::iterator(MI)),
1299 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1301 // Next, add the true and fallthrough blocks as its successors.
1302 BB->addSuccessor(copy0MBB);
1303 BB->addSuccessor(sinkMBB);
1305 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1306 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1309 // %FalseValue = ...
1310 // # fallthrough to sinkMBB
1313 // Update machine-CFG edges
1314 BB->addSuccessor(sinkMBB);
1317 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1320 BuildMI(*BB, BB->begin(), dl,
1321 TII.get(XCore::PHI), MI->getOperand(0).getReg())
1322 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1323 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1325 MI->eraseFromParent(); // The pseudo instruction is gone now.
1329 //===----------------------------------------------------------------------===//
1330 // Target Optimization Hooks
1331 //===----------------------------------------------------------------------===//
1333 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1334 DAGCombinerInfo &DCI) const {
1335 SelectionDAG &DAG = DCI.DAG;
1336 DebugLoc dl = N->getDebugLoc();
1337 switch (N->getOpcode()) {
1339 case XCoreISD::LADD: {
1340 SDValue N0 = N->getOperand(0);
1341 SDValue N1 = N->getOperand(1);
1342 SDValue N2 = N->getOperand(2);
1343 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1345 EVT VT = N0.getValueType();
1347 // canonicalize constant to RHS
1349 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1351 // fold (ladd 0, 0, x) -> 0, x & 1
1352 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1353 SDValue Carry = DAG.getConstant(0, VT);
1354 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1355 DAG.getConstant(1, VT));
1356 SDValue Ops [] = { Carry, Result };
1357 return DAG.getMergeValues(Ops, 2, dl);
1360 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1362 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1363 APInt KnownZero, KnownOne;
1364 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1365 VT.getSizeInBits() - 1);
1366 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne);
1367 if ((KnownZero & Mask) == Mask) {
1368 SDValue Carry = DAG.getConstant(0, VT);
1369 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1370 SDValue Ops [] = { Carry, Result };
1371 return DAG.getMergeValues(Ops, 2, dl);
1376 case XCoreISD::LSUB: {
1377 SDValue N0 = N->getOperand(0);
1378 SDValue N1 = N->getOperand(1);
1379 SDValue N2 = N->getOperand(2);
1380 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1381 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1382 EVT VT = N0.getValueType();
1384 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1385 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1386 APInt KnownZero, KnownOne;
1387 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1388 VT.getSizeInBits() - 1);
1389 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne);
1390 if ((KnownZero & Mask) == Mask) {
1391 SDValue Borrow = N2;
1392 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1393 DAG.getConstant(0, VT), N2);
1394 SDValue Ops [] = { Borrow, Result };
1395 return DAG.getMergeValues(Ops, 2, dl);
1399 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1401 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1402 APInt KnownZero, KnownOne;
1403 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1404 VT.getSizeInBits() - 1);
1405 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne);
1406 if ((KnownZero & Mask) == Mask) {
1407 SDValue Borrow = DAG.getConstant(0, VT);
1408 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1409 SDValue Ops [] = { Borrow, Result };
1410 return DAG.getMergeValues(Ops, 2, dl);
1415 case XCoreISD::LMUL: {
1416 SDValue N0 = N->getOperand(0);
1417 SDValue N1 = N->getOperand(1);
1418 SDValue N2 = N->getOperand(2);
1419 SDValue N3 = N->getOperand(3);
1420 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1421 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1422 EVT VT = N0.getValueType();
1423 // Canonicalize multiplicative constant to RHS. If both multiplicative
1424 // operands are constant canonicalize smallest to RHS.
1425 if ((N0C && !N1C) ||
1426 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1427 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1431 if (N1C && N1C->isNullValue()) {
1432 // If the high result is unused fold to add(a, b)
1433 if (N->hasNUsesOfValue(0, 0)) {
1434 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1435 SDValue Ops [] = { Lo, Lo };
1436 return DAG.getMergeValues(Ops, 2, dl);
1438 // Otherwise fold to ladd(a, b, 0)
1439 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1444 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1445 // lmul(x, y, a, b). The high result of lmul will be ignored.
1446 // This is only profitable if the intermediate results are unused
1448 SDValue Mul0, Mul1, Addend0, Addend1;
1449 if (N->getValueType(0) == MVT::i32 &&
1450 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1451 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1452 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1453 Mul1, Addend0, Addend1);
1454 SDValue Result(Ignored.getNode(), 1);
1457 APInt HighMask = APInt::getHighBitsSet(64, 32);
1458 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1459 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1460 // before type legalization as it is messy to match the operands after
1462 if (N->getValueType(0) == MVT::i64 &&
1463 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1464 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1465 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1466 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1467 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1468 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1469 Mul0, DAG.getConstant(0, MVT::i32));
1470 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1471 Mul1, DAG.getConstant(0, MVT::i32));
1472 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1473 Addend0, DAG.getConstant(0, MVT::i32));
1474 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1475 Addend1, DAG.getConstant(0, MVT::i32));
1476 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1477 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1478 Addend0L, Addend1L);
1479 SDValue Lo(Hi.getNode(), 1);
1480 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1485 // Replace unaligned store of unaligned load with memmove.
1486 StoreSDNode *ST = cast<StoreSDNode>(N);
1487 if (!DCI.isBeforeLegalize() ||
1488 allowsUnalignedMemoryAccesses(ST->getMemoryVT()) ||
1489 ST->isVolatile() || ST->isIndexed()) {
1492 SDValue Chain = ST->getChain();
1494 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1495 if (StoreBits % 8) {
1498 unsigned ABIAlignment = getTargetData()->getABITypeAlignment(
1499 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1500 unsigned Alignment = ST->getAlignment();
1501 if (Alignment >= ABIAlignment) {
1505 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1506 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1507 LD->getAlignment() == Alignment &&
1508 !LD->isVolatile() && !LD->isIndexed() &&
1509 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1510 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1512 DAG.getConstant(StoreBits/8, MVT::i32),
1513 Alignment, false, ST->getPointerInfo(),
1514 LD->getPointerInfo());
1523 void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1526 const SelectionDAG &DAG,
1527 unsigned Depth) const {
1528 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1529 switch (Op.getOpcode()) {
1531 case XCoreISD::LADD:
1532 case XCoreISD::LSUB:
1533 if (Op.getResNo() == 0) {
1534 // Top bits of carry / borrow are clear.
1535 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
1536 KnownZero.getBitWidth() - 1);
1542 //===----------------------------------------------------------------------===//
1543 // Addressing mode description hooks
1544 //===----------------------------------------------------------------------===//
1546 static inline bool isImmUs(int64_t val)
1548 return (val >= 0 && val <= 11);
1551 static inline bool isImmUs2(int64_t val)
1553 return (val%2 == 0 && isImmUs(val/2));
1556 static inline bool isImmUs4(int64_t val)
1558 return (val%4 == 0 && isImmUs(val/4));
1561 /// isLegalAddressingMode - Return true if the addressing mode represented
1562 /// by AM is legal for this target, for a load/store of the specified type.
1564 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1566 if (Ty->getTypeID() == Type::VoidTyID)
1567 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1569 const TargetData *TD = TM.getTargetData();
1570 unsigned Size = TD->getTypeAllocSize(Ty);
1572 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1579 if (AM.Scale == 0) {
1580 return isImmUs(AM.BaseOffs);
1583 return AM.Scale == 1 && AM.BaseOffs == 0;
1587 if (AM.Scale == 0) {
1588 return isImmUs2(AM.BaseOffs);
1591 return AM.Scale == 2 && AM.BaseOffs == 0;
1594 if (AM.Scale == 0) {
1595 return isImmUs4(AM.BaseOffs);
1598 return AM.Scale == 4 && AM.BaseOffs == 0;
1602 //===----------------------------------------------------------------------===//
1603 // XCore Inline Assembly Support
1604 //===----------------------------------------------------------------------===//
1606 std::pair<unsigned, const TargetRegisterClass*>
1607 XCoreTargetLowering::
1608 getRegForInlineAsmConstraint(const std::string &Constraint,
1610 if (Constraint.size() == 1) {
1611 switch (Constraint[0]) {
1614 return std::make_pair(0U, XCore::GRRegsRegisterClass);
1617 // Use the default implementation in TargetLowering to convert the register
1618 // constraint into a member of a register class.
1619 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);