1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef XCOREISELLOWERING_H
16 #define XCOREISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Store word to stack
48 // Corresponds to retsp instruction
51 // Corresponds to LADD instruction
54 // Corresponds to LSUB instruction
57 // Corresponds to LMUL instruction
60 // Corresponds to MACCU instruction
63 // Corresponds to MACCS instruction
66 // Corresponds to CRC8 instruction
72 // Jumptable branch using long branches for each entry.
75 // Offset from frame pointer to the first (possible) on-stack argument
78 // Exception handler return. The stack is restored to the first
79 // followed by a jump to the second argument.
87 //===--------------------------------------------------------------------===//
88 // TargetLowering Implementation
89 //===--------------------------------------------------------------------===//
90 class XCoreTargetLowering : public TargetLowering
94 explicit XCoreTargetLowering(XCoreTargetMachine &TM);
96 using TargetLowering::isZExtFree;
97 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
100 virtual unsigned getJumpTableEncoding() const;
101 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
103 /// LowerOperation - Provide custom lowering hooks for some operations.
104 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
106 /// ReplaceNodeResults - Replace the results of node with an illegal result
107 /// type with new values built out of custom code.
109 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
110 SelectionDAG &DAG) const;
112 /// getTargetNodeName - This method returns the name of a target specific
114 virtual const char *getTargetNodeName(unsigned Opcode) const;
116 virtual MachineBasicBlock *
117 EmitInstrWithCustomInserter(MachineInstr *MI,
118 MachineBasicBlock *MBB) const;
120 virtual bool isLegalAddressingMode(const AddrMode &AM,
124 const XCoreTargetMachine &TM;
125 const XCoreSubtarget &Subtarget;
127 // Lower Operand helpers
128 SDValue LowerCCCArguments(SDValue Chain,
129 CallingConv::ID CallConv,
131 const SmallVectorImpl<ISD::InputArg> &Ins,
132 SDLoc dl, SelectionDAG &DAG,
133 SmallVectorImpl<SDValue> &InVals) const;
134 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
135 CallingConv::ID CallConv, bool isVarArg,
137 const SmallVectorImpl<ISD::OutputArg> &Outs,
138 const SmallVectorImpl<SDValue> &OutVals,
139 const SmallVectorImpl<ISD::InputArg> &Ins,
140 SDLoc dl, SelectionDAG &DAG,
141 SmallVectorImpl<SDValue> &InVals) const;
142 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
143 CallingConv::ID CallConv, bool isVarArg,
144 const SmallVectorImpl<ISD::InputArg> &Ins,
145 SDLoc dl, SelectionDAG &DAG,
146 SmallVectorImpl<SDValue> &InVals) const;
147 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
148 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
149 SelectionDAG &DAG) const;
150 SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
151 SDValue Base, int64_t Offset,
152 SelectionDAG &DAG) const;
154 // Lower Operand specifics
155 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
164 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
165 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
166 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
173 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
174 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
176 // Inline asm support
177 std::pair<unsigned, const TargetRegisterClass*>
178 getRegForInlineAsmConstraint(const std::string &Constraint,
182 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
183 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
185 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
187 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
190 const SelectionDAG &DAG,
191 unsigned Depth = 0) const;
194 LowerFormalArguments(SDValue Chain,
195 CallingConv::ID CallConv,
197 const SmallVectorImpl<ISD::InputArg> &Ins,
198 SDLoc dl, SelectionDAG &DAG,
199 SmallVectorImpl<SDValue> &InVals) const;
202 LowerCall(TargetLowering::CallLoweringInfo &CLI,
203 SmallVectorImpl<SDValue> &InVals) const;
206 LowerReturn(SDValue Chain,
207 CallingConv::ID CallConv, bool isVarArg,
208 const SmallVectorImpl<ISD::OutputArg> &Outs,
209 const SmallVectorImpl<SDValue> &OutVals,
210 SDLoc dl, SelectionDAG &DAG) const;
213 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
215 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
216 LLVMContext &Context) const;
220 #endif // XCOREISELLOWERING_H