1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
16 #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Load word from stack
48 // Store word to stack
51 // Corresponds to retsp instruction
54 // Corresponds to LADD instruction
57 // Corresponds to LSUB instruction
60 // Corresponds to LMUL instruction
63 // Corresponds to MACCU instruction
66 // Corresponds to MACCS instruction
69 // Corresponds to CRC8 instruction
75 // Jumptable branch using long branches for each entry.
78 // Offset from frame pointer to the first (possible) on-stack argument
81 // Exception handler return. The stack is restored to the first
82 // followed by a jump to the second argument.
90 //===--------------------------------------------------------------------===//
91 // TargetLowering Implementation
92 //===--------------------------------------------------------------------===//
93 class XCoreTargetLowering : public TargetLowering
96 explicit XCoreTargetLowering(const TargetMachine &TM,
97 const XCoreSubtarget &Subtarget);
99 using TargetLowering::isZExtFree;
100 bool isZExtFree(SDValue Val, EVT VT2) const override;
103 unsigned getJumpTableEncoding() const override;
104 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
106 /// LowerOperation - Provide custom lowering hooks for some operations.
107 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
109 /// ReplaceNodeResults - Replace the results of node with an illegal result
110 /// type with new values built out of custom code.
112 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
113 SelectionDAG &DAG) const override;
115 /// getTargetNodeName - This method returns the name of a target specific
117 const char *getTargetNodeName(unsigned Opcode) const override;
120 EmitInstrWithCustomInserter(MachineInstr *MI,
121 MachineBasicBlock *MBB) const override;
123 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
124 unsigned AS) const override;
127 const TargetMachine &TM;
128 const XCoreSubtarget &Subtarget;
130 // Lower Operand helpers
131 SDValue LowerCCCArguments(SDValue Chain,
132 CallingConv::ID CallConv,
134 const SmallVectorImpl<ISD::InputArg> &Ins,
135 SDLoc dl, SelectionDAG &DAG,
136 SmallVectorImpl<SDValue> &InVals) const;
137 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
138 CallingConv::ID CallConv, bool isVarArg,
140 const SmallVectorImpl<ISD::OutputArg> &Outs,
141 const SmallVectorImpl<SDValue> &OutVals,
142 const SmallVectorImpl<ISD::InputArg> &Ins,
143 SDLoc dl, SelectionDAG &DAG,
144 SmallVectorImpl<SDValue> &InVals) const;
145 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
146 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
147 SelectionDAG &DAG) const;
148 SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
149 SDValue Base, int64_t Offset,
150 SelectionDAG &DAG) const;
152 // Lower Operand specifics
153 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
154 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
164 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
165 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
166 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
173 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
175 // Inline asm support
176 std::pair<unsigned, const TargetRegisterClass *>
177 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
178 StringRef Constraint, MVT VT) const override;
181 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
182 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
184 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
186 void computeKnownBitsForTargetNode(const SDValue Op,
189 const SelectionDAG &DAG,
190 unsigned Depth = 0) const override;
193 LowerFormalArguments(SDValue Chain,
194 CallingConv::ID CallConv,
196 const SmallVectorImpl<ISD::InputArg> &Ins,
197 SDLoc dl, SelectionDAG &DAG,
198 SmallVectorImpl<SDValue> &InVals) const override;
201 LowerCall(TargetLowering::CallLoweringInfo &CLI,
202 SmallVectorImpl<SDValue> &InVals) const override;
205 LowerReturn(SDValue Chain,
206 CallingConv::ID CallConv, bool isVarArg,
207 const SmallVectorImpl<ISD::OutputArg> &Outs,
208 const SmallVectorImpl<SDValue> &OutVals,
209 SDLoc dl, SelectionDAG &DAG) const override;
212 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
214 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
215 LLVMContext &Context) const override;