1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef XCOREISELLOWERING_H
16 #define XCOREISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Store word to stack
48 // Corresponds to retsp instruction
51 // Corresponds to LADD instruction
54 // Corresponds to LSUB instruction
57 // Corresponds to LMUL instruction
60 // Corresponds to MACCU instruction
63 // Corresponds to MACCS instruction
69 // Jumptable branch using long branches for each entry.
74 //===--------------------------------------------------------------------===//
75 // TargetLowering Implementation
76 //===--------------------------------------------------------------------===//
77 class XCoreTargetLowering : public TargetLowering
81 explicit XCoreTargetLowering(XCoreTargetMachine &TM);
83 virtual unsigned getJumpTableEncoding() const;
84 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
86 /// LowerOperation - Provide custom lowering hooks for some operations.
87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
89 /// ReplaceNodeResults - Replace the results of node with an illegal result
90 /// type with new values built out of custom code.
92 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
93 SelectionDAG &DAG) const;
95 /// getTargetNodeName - This method returns the name of a target specific
97 virtual const char *getTargetNodeName(unsigned Opcode) const;
99 virtual MachineBasicBlock *
100 EmitInstrWithCustomInserter(MachineInstr *MI,
101 MachineBasicBlock *MBB) const;
103 virtual bool isLegalAddressingMode(const AddrMode &AM,
107 const XCoreTargetMachine &TM;
108 const XCoreSubtarget &Subtarget;
110 // Lower Operand helpers
111 SDValue LowerCCCArguments(SDValue Chain,
112 CallingConv::ID CallConv,
114 const SmallVectorImpl<ISD::InputArg> &Ins,
115 DebugLoc dl, SelectionDAG &DAG,
116 SmallVectorImpl<SDValue> &InVals) const;
117 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
118 CallingConv::ID CallConv, bool isVarArg,
120 const SmallVectorImpl<ISD::OutputArg> &Outs,
121 const SmallVectorImpl<SDValue> &OutVals,
122 const SmallVectorImpl<ISD::InputArg> &Ins,
123 DebugLoc dl, SelectionDAG &DAG,
124 SmallVectorImpl<SDValue> &InVals) const;
125 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
126 CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
128 DebugLoc dl, SelectionDAG &DAG,
129 SmallVectorImpl<SDValue> &InVals) const;
130 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
131 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
132 SelectionDAG &DAG) const;
134 // Lower Operand specifics
135 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
150 // Inline asm support
151 std::pair<unsigned, const TargetRegisterClass*>
152 getRegForInlineAsmConstraint(const std::string &Constraint,
156 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
157 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
159 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
161 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
165 const SelectionDAG &DAG,
166 unsigned Depth = 0) const;
169 LowerFormalArguments(SDValue Chain,
170 CallingConv::ID CallConv,
172 const SmallVectorImpl<ISD::InputArg> &Ins,
173 DebugLoc dl, SelectionDAG &DAG,
174 SmallVectorImpl<SDValue> &InVals) const;
177 LowerCall(SDValue Chain, SDValue Callee,
178 CallingConv::ID CallConv, bool isVarArg,
180 const SmallVectorImpl<ISD::OutputArg> &Outs,
181 const SmallVectorImpl<SDValue> &OutVals,
182 const SmallVectorImpl<ISD::InputArg> &Ins,
183 DebugLoc dl, SelectionDAG &DAG,
184 SmallVectorImpl<SDValue> &InVals) const;
187 LowerReturn(SDValue Chain,
188 CallingConv::ID CallConv, bool isVarArg,
189 const SmallVectorImpl<ISD::OutputArg> &Outs,
190 const SmallVectorImpl<SDValue> &OutVals,
191 DebugLoc dl, SelectionDAG &DAG) const;
194 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
196 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
197 LLVMContext &Context) const;
201 #endif // XCOREISELLOWERING_H