1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef XCOREISELLOWERING_H
16 #define XCOREISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Store word to stack
48 // Corresponds to retsp instruction
51 // Corresponds to LADD instruction
54 // Corresponds to LSUB instruction
57 // Corresponds to LMUL instruction
60 // Corresponds to MACCU instruction
63 // Corresponds to MACCS instruction
69 // Jumptable branch using long branches for each entry.
74 //===--------------------------------------------------------------------===//
75 // TargetLowering Implementation
76 //===--------------------------------------------------------------------===//
77 class XCoreTargetLowering : public TargetLowering
81 explicit XCoreTargetLowering(XCoreTargetMachine &TM);
83 virtual unsigned getJumpTableEncoding() const;
85 /// LowerOperation - Provide custom lowering hooks for some operations.
86 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
88 /// ReplaceNodeResults - Replace the results of node with an illegal result
89 /// type with new values built out of custom code.
91 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
92 SelectionDAG &DAG) const;
94 /// getTargetNodeName - This method returns the name of a target specific
96 virtual const char *getTargetNodeName(unsigned Opcode) const;
98 virtual MachineBasicBlock *
99 EmitInstrWithCustomInserter(MachineInstr *MI,
100 MachineBasicBlock *MBB) const;
102 virtual bool isLegalAddressingMode(const AddrMode &AM,
103 const Type *Ty) const;
105 /// getFunctionAlignment - Return the Log2 alignment of this function.
106 virtual unsigned getFunctionAlignment(const Function *F) const;
109 const XCoreTargetMachine &TM;
110 const XCoreSubtarget &Subtarget;
112 // Lower Operand helpers
113 SDValue LowerCCCArguments(SDValue Chain,
114 CallingConv::ID CallConv,
116 const SmallVectorImpl<ISD::InputArg> &Ins,
117 DebugLoc dl, SelectionDAG &DAG,
118 SmallVectorImpl<SDValue> &InVals) const;
119 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
120 CallingConv::ID CallConv, bool isVarArg,
122 const SmallVectorImpl<ISD::OutputArg> &Outs,
123 const SmallVectorImpl<SDValue> &OutVals,
124 const SmallVectorImpl<ISD::InputArg> &Ins,
125 DebugLoc dl, SelectionDAG &DAG,
126 SmallVectorImpl<SDValue> &InVals) const;
127 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
128 CallingConv::ID CallConv, bool isVarArg,
129 const SmallVectorImpl<ISD::InputArg> &Ins,
130 DebugLoc dl, SelectionDAG &DAG,
131 SmallVectorImpl<SDValue> &InVals) const;
132 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
133 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
134 SelectionDAG &DAG) const;
136 // Lower Operand specifics
137 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
142 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
143 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
145 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
151 // Inline asm support
152 std::vector<unsigned>
153 getRegClassForInlineAsmConstraint(const std::string &Constraint,
157 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
158 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
160 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
162 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
166 const SelectionDAG &DAG,
167 unsigned Depth = 0) const;
170 LowerFormalArguments(SDValue Chain,
171 CallingConv::ID CallConv,
173 const SmallVectorImpl<ISD::InputArg> &Ins,
174 DebugLoc dl, SelectionDAG &DAG,
175 SmallVectorImpl<SDValue> &InVals) const;
178 LowerCall(SDValue Chain, SDValue Callee,
179 CallingConv::ID CallConv, bool isVarArg,
181 const SmallVectorImpl<ISD::OutputArg> &Outs,
182 const SmallVectorImpl<SDValue> &OutVals,
183 const SmallVectorImpl<ISD::InputArg> &Ins,
184 DebugLoc dl, SelectionDAG &DAG,
185 SmallVectorImpl<SDValue> &InVals) const;
188 LowerReturn(SDValue Chain,
189 CallingConv::ID CallConv, bool isVarArg,
190 const SmallVectorImpl<ISD::OutputArg> &Outs,
191 const SmallVectorImpl<SDValue> &OutVals,
192 DebugLoc dl, SelectionDAG &DAG) const;
195 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
196 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
197 LLVMContext &Context) const;
201 #endif // XCOREISELLOWERING_H