1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef XCOREISELLOWERING_H
16 #define XCOREISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Store word to stack
48 // Corresponds to retsp instruction
51 // Corresponds to LADD instruction
54 // Corresponds to LSUB instruction
57 // Corresponds to LMUL instruction
60 // Corresponds to MACCU instruction
63 // Corresponds to MACCS instruction
69 // Jumptable branch using long branches for each entry.
74 //===--------------------------------------------------------------------===//
75 // TargetLowering Implementation
76 //===--------------------------------------------------------------------===//
77 class XCoreTargetLowering : public TargetLowering
81 explicit XCoreTargetLowering(XCoreTargetMachine &TM);
83 /// LowerOperation - Provide custom lowering hooks for some operations.
84 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
86 /// ReplaceNodeResults - Replace the results of node with an illegal result
87 /// type with new values built out of custom code.
89 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
92 /// getTargetNodeName - This method returns the name of a target specific
94 virtual const char *getTargetNodeName(unsigned Opcode) const;
96 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
97 MachineBasicBlock *MBB,
98 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
100 virtual bool isLegalAddressingMode(const AddrMode &AM,
101 const Type *Ty) const;
103 /// getFunctionAlignment - Return the Log2 alignment of this function.
104 virtual unsigned getFunctionAlignment(const Function *F) const;
107 const XCoreTargetMachine &TM;
108 const XCoreSubtarget &Subtarget;
110 // Lower Operand helpers
111 SDValue LowerCCCArguments(SDValue Chain,
112 CallingConv::ID CallConv,
114 const SmallVectorImpl<ISD::InputArg> &Ins,
115 DebugLoc dl, SelectionDAG &DAG,
116 SmallVectorImpl<SDValue> &InVals);
117 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
118 CallingConv::ID CallConv, bool isVarArg,
120 const SmallVectorImpl<ISD::OutputArg> &Outs,
121 const SmallVectorImpl<ISD::InputArg> &Ins,
122 DebugLoc dl, SelectionDAG &DAG,
123 SmallVectorImpl<SDValue> &InVals);
124 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
125 CallingConv::ID CallConv, bool isVarArg,
126 const SmallVectorImpl<ISD::InputArg> &Ins,
127 DebugLoc dl, SelectionDAG &DAG,
128 SmallVectorImpl<SDValue> &InVals);
129 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
130 SDValue getGlobalAddressWrapper(SDValue GA, GlobalValue *GV,
133 // Lower Operand specifics
134 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG);
135 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG);
136 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
137 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
138 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
139 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
140 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
141 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
142 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
143 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
144 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG);
145 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG);
146 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
148 // Inline asm support
149 std::vector<unsigned>
150 getRegClassForInlineAsmConstraint(const std::string &Constraint,
154 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG);
155 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
157 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
159 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
163 const SelectionDAG &DAG,
164 unsigned Depth = 0) const;
167 LowerFormalArguments(SDValue Chain,
168 CallingConv::ID CallConv,
170 const SmallVectorImpl<ISD::InputArg> &Ins,
171 DebugLoc dl, SelectionDAG &DAG,
172 SmallVectorImpl<SDValue> &InVals);
175 LowerCall(SDValue Chain, SDValue Callee,
176 CallingConv::ID CallConv, bool isVarArg,
178 const SmallVectorImpl<ISD::OutputArg> &Outs,
179 const SmallVectorImpl<ISD::InputArg> &Ins,
180 DebugLoc dl, SelectionDAG &DAG,
181 SmallVectorImpl<SDValue> &InVals);
184 LowerReturn(SDValue Chain,
185 CallingConv::ID CallConv, bool isVarArg,
186 const SmallVectorImpl<ISD::OutputArg> &Outs,
187 DebugLoc dl, SelectionDAG &DAG);
190 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
191 const SmallVectorImpl<EVT> &OutTys,
192 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
197 #endif // XCOREISELLOWERING_H