1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef XCOREISELLOWERING_H
16 #define XCOREISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Store word to stack
48 // Corresponds to retsp instruction
51 // Corresponds to LADD instruction
54 // Corresponds to LSUB instruction
57 // Corresponds to LMUL instruction
60 // Corresponds to MACCU instruction
63 // Corresponds to MACCS instruction
66 // Corresponds to CRC8 instruction
72 // Jumptable branch using long branches for each entry.
77 //===--------------------------------------------------------------------===//
78 // TargetLowering Implementation
79 //===--------------------------------------------------------------------===//
80 class XCoreTargetLowering : public TargetLowering
84 explicit XCoreTargetLowering(XCoreTargetMachine &TM);
86 using TargetLowering::isZExtFree;
87 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
90 virtual unsigned getJumpTableEncoding() const;
91 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
93 /// LowerOperation - Provide custom lowering hooks for some operations.
94 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
96 /// ReplaceNodeResults - Replace the results of node with an illegal result
97 /// type with new values built out of custom code.
99 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
100 SelectionDAG &DAG) const;
102 /// getTargetNodeName - This method returns the name of a target specific
104 virtual const char *getTargetNodeName(unsigned Opcode) const;
106 virtual MachineBasicBlock *
107 EmitInstrWithCustomInserter(MachineInstr *MI,
108 MachineBasicBlock *MBB) const;
110 virtual bool isLegalAddressingMode(const AddrMode &AM,
114 const XCoreTargetMachine &TM;
115 const XCoreSubtarget &Subtarget;
117 // Lower Operand helpers
118 SDValue LowerCCCArguments(SDValue Chain,
119 CallingConv::ID CallConv,
121 const SmallVectorImpl<ISD::InputArg> &Ins,
122 SDLoc dl, SelectionDAG &DAG,
123 SmallVectorImpl<SDValue> &InVals) const;
124 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
125 CallingConv::ID CallConv, bool isVarArg,
127 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<SDValue> &OutVals,
129 const SmallVectorImpl<ISD::InputArg> &Ins,
130 SDLoc dl, SelectionDAG &DAG,
131 SmallVectorImpl<SDValue> &InVals) const;
132 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
133 CallingConv::ID CallConv, bool isVarArg,
134 const SmallVectorImpl<ISD::InputArg> &Ins,
135 SDLoc dl, SelectionDAG &DAG,
136 SmallVectorImpl<SDValue> &InVals) const;
137 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
138 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
139 SelectionDAG &DAG) const;
140 SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
141 SDValue Base, int64_t Offset,
142 SelectionDAG &DAG) const;
144 // Lower Operand specifics
145 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
146 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
147 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
148 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
149 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
150 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
151 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
152 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
153 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
154 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
162 // Inline asm support
163 std::pair<unsigned, const TargetRegisterClass*>
164 getRegForInlineAsmConstraint(const std::string &Constraint,
168 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
169 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
171 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
173 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
176 const SelectionDAG &DAG,
177 unsigned Depth = 0) const;
180 LowerFormalArguments(SDValue Chain,
181 CallingConv::ID CallConv,
183 const SmallVectorImpl<ISD::InputArg> &Ins,
184 SDLoc dl, SelectionDAG &DAG,
185 SmallVectorImpl<SDValue> &InVals) const;
188 LowerCall(TargetLowering::CallLoweringInfo &CLI,
189 SmallVectorImpl<SDValue> &InVals) const;
192 LowerReturn(SDValue Chain,
193 CallingConv::ID CallConv, bool isVarArg,
194 const SmallVectorImpl<ISD::OutputArg> &Outs,
195 const SmallVectorImpl<SDValue> &OutVals,
196 SDLoc dl, SelectionDAG &DAG) const;
199 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
201 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
202 LLVMContext &Context) const;
206 #endif // XCOREISELLOWERING_H