1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
16 #define LLVM_LIB_TARGET_XCORE_XCOREISELLOWERING_H
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
29 enum NodeType : unsigned {
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Load word from stack
48 // Store word to stack
51 // Corresponds to retsp instruction
54 // Corresponds to LADD instruction
57 // Corresponds to LSUB instruction
60 // Corresponds to LMUL instruction
63 // Corresponds to MACCU instruction
66 // Corresponds to MACCS instruction
69 // Corresponds to CRC8 instruction
75 // Jumptable branch using long branches for each entry.
78 // Offset from frame pointer to the first (possible) on-stack argument
81 // Exception handler return. The stack is restored to the first
82 // followed by a jump to the second argument.
90 //===--------------------------------------------------------------------===//
91 // TargetLowering Implementation
92 //===--------------------------------------------------------------------===//
93 class XCoreTargetLowering : public TargetLowering
96 explicit XCoreTargetLowering(const TargetMachine &TM,
97 const XCoreSubtarget &Subtarget);
99 using TargetLowering::isZExtFree;
100 bool isZExtFree(SDValue Val, EVT VT2) const override;
103 unsigned getJumpTableEncoding() const override;
104 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override {
108 /// LowerOperation - Provide custom lowering hooks for some operations.
109 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
111 /// ReplaceNodeResults - Replace the results of node with an illegal result
112 /// type with new values built out of custom code.
114 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
115 SelectionDAG &DAG) const override;
117 /// getTargetNodeName - This method returns the name of a target specific
119 const char *getTargetNodeName(unsigned Opcode) const override;
122 EmitInstrWithCustomInserter(MachineInstr *MI,
123 MachineBasicBlock *MBB) const override;
125 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
126 Type *Ty, unsigned AS) const override;
129 const TargetMachine &TM;
130 const XCoreSubtarget &Subtarget;
132 // Lower Operand helpers
133 SDValue LowerCCCArguments(SDValue Chain,
134 CallingConv::ID CallConv,
136 const SmallVectorImpl<ISD::InputArg> &Ins,
137 SDLoc dl, SelectionDAG &DAG,
138 SmallVectorImpl<SDValue> &InVals) const;
139 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
140 CallingConv::ID CallConv, bool isVarArg,
142 const SmallVectorImpl<ISD::OutputArg> &Outs,
143 const SmallVectorImpl<SDValue> &OutVals,
144 const SmallVectorImpl<ISD::InputArg> &Ins,
145 SDLoc dl, SelectionDAG &DAG,
146 SmallVectorImpl<SDValue> &InVals) const;
147 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
148 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
149 SelectionDAG &DAG) const;
150 SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
151 SDValue Base, int64_t Offset,
152 SelectionDAG &DAG) const;
154 // Lower Operand specifics
155 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
161 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
162 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
163 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
164 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
165 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
166 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
173 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
174 SDValue LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
177 // Inline asm support
178 std::pair<unsigned, const TargetRegisterClass *>
179 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
180 StringRef Constraint, MVT VT) const override;
183 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
184 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
186 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
188 void computeKnownBitsForTargetNode(const SDValue Op,
191 const SelectionDAG &DAG,
192 unsigned Depth = 0) const override;
195 LowerFormalArguments(SDValue Chain,
196 CallingConv::ID CallConv,
198 const SmallVectorImpl<ISD::InputArg> &Ins,
199 SDLoc dl, SelectionDAG &DAG,
200 SmallVectorImpl<SDValue> &InVals) const override;
203 LowerCall(TargetLowering::CallLoweringInfo &CLI,
204 SmallVectorImpl<SDValue> &InVals) const override;
207 LowerReturn(SDValue Chain,
208 CallingConv::ID CallConv, bool isVarArg,
209 const SmallVectorImpl<ISD::OutputArg> &Outs,
210 const SmallVectorImpl<SDValue> &OutVals,
211 SDLoc dl, SelectionDAG &DAG) const override;
214 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
216 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
217 LLVMContext &Context) const override;