1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreInstrInfo.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/IR/Constants.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "XCoreGenInstrInfo.inc"
34 // XCore Condition Codes
46 // Pin the vtable to this file.
47 void XCoreInstrInfo::anchor() {}
49 XCoreInstrInfo::XCoreInstrInfo()
50 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
54 static bool isZeroImm(const MachineOperand &op) {
55 return op.isImm() && op.getImm() == 0;
58 /// isLoadFromStackSlot - If the specified machine instruction is a direct
59 /// load from a stack slot, return the virtual or physical register number of
60 /// the destination along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than loading from the stack slot.
64 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
65 int Opcode = MI->getOpcode();
66 if (Opcode == XCore::LDWFI)
68 if ((MI->getOperand(1).isFI()) && // is a stack slot
69 (MI->getOperand(2).isImm()) && // the imm is zero
70 (isZeroImm(MI->getOperand(2))))
72 FrameIndex = MI->getOperand(1).getIndex();
73 return MI->getOperand(0).getReg();
79 /// isStoreToStackSlot - If the specified machine instruction is a direct
80 /// store to a stack slot, return the virtual or physical register number of
81 /// the source reg along with the FrameIndex of the loaded stack slot. If
82 /// not, return 0. This predicate must return 0 if the instruction has
83 /// any side effects other than storing to the stack slot.
85 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
86 int &FrameIndex) const {
87 int Opcode = MI->getOpcode();
88 if (Opcode == XCore::STWFI)
90 if ((MI->getOperand(1).isFI()) && // is a stack slot
91 (MI->getOperand(2).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(2))))
94 FrameIndex = MI->getOperand(1).getIndex();
95 return MI->getOperand(0).getReg();
101 //===----------------------------------------------------------------------===//
103 //===----------------------------------------------------------------------===//
105 static inline bool IsBRU(unsigned BrOpc) {
106 return BrOpc == XCore::BRFU_u6
107 || BrOpc == XCore::BRFU_lu6
108 || BrOpc == XCore::BRBU_u6
109 || BrOpc == XCore::BRBU_lu6;
112 static inline bool IsBRT(unsigned BrOpc) {
113 return BrOpc == XCore::BRFT_ru6
114 || BrOpc == XCore::BRFT_lru6
115 || BrOpc == XCore::BRBT_ru6
116 || BrOpc == XCore::BRBT_lru6;
119 static inline bool IsBRF(unsigned BrOpc) {
120 return BrOpc == XCore::BRFF_ru6
121 || BrOpc == XCore::BRFF_lru6
122 || BrOpc == XCore::BRBF_ru6
123 || BrOpc == XCore::BRBF_lru6;
126 static inline bool IsCondBranch(unsigned BrOpc) {
127 return IsBRF(BrOpc) || IsBRT(BrOpc);
130 static inline bool IsBR_JT(unsigned BrOpc) {
131 return BrOpc == XCore::BR_JT
132 || BrOpc == XCore::BR_JT32;
135 /// GetCondFromBranchOpc - Return the XCore CC that matches
136 /// the correspondent Branch instruction opcode.
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
140 return XCore::COND_TRUE;
141 } else if (IsBRF(BrOpc)) {
142 return XCore::COND_FALSE;
144 return XCore::COND_INVALID;
148 /// GetCondBranchFromCond - Return the Branch instruction
149 /// opcode that matches the cc.
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
153 default: llvm_unreachable("Illegal condition code!");
154 case XCore::COND_TRUE : return XCore::BRFT_lru6;
155 case XCore::COND_FALSE : return XCore::BRFF_lru6;
159 /// GetOppositeBranchCondition - Return the inverse of the specified
160 /// condition, e.g. turning COND_E to COND_NE.
161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
164 default: llvm_unreachable("Illegal condition code!");
165 case XCore::COND_TRUE : return XCore::COND_FALSE;
166 case XCore::COND_FALSE : return XCore::COND_TRUE;
170 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
171 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
172 /// implemented for a target). Upon success, this returns false and returns
173 /// with the following information in various cases:
175 /// 1. If this block ends with no branches (it just falls through to its succ)
176 /// just return false, leaving TBB/FBB null.
177 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
178 /// the destination block.
179 /// 3. If this block ends with an conditional branch and it falls through to
180 /// an successor block, it sets TBB to be the branch destination block and a
181 /// list of operands that evaluate the condition. These
182 /// operands can be passed to other TargetInstrInfo methods to create new
184 /// 4. If this block ends with an conditional branch and an unconditional
185 /// block, it returns the 'true' destination in TBB, the 'false' destination
186 /// in FBB, and a list of operands that evaluate the condition. These
187 /// operands can be passed to other TargetInstrInfo methods to create new
190 /// Note that RemoveBranch and InsertBranch must be implemented to support
191 /// cases where this method returns success.
194 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
195 MachineBasicBlock *&FBB,
196 SmallVectorImpl<MachineOperand> &Cond,
197 bool AllowModify) const {
198 // If the block has no terminators, it just falls into the block after it.
199 MachineBasicBlock::iterator I = MBB.end();
200 if (I == MBB.begin())
203 while (I->isDebugValue()) {
204 if (I == MBB.begin())
208 if (!isUnpredicatedTerminator(I))
211 // Get the last instruction in the block.
212 MachineInstr *LastInst = I;
214 // If there is only one terminator instruction, process it.
215 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
216 if (IsBRU(LastInst->getOpcode())) {
217 TBB = LastInst->getOperand(0).getMBB();
221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
222 if (BranchCode == XCore::COND_INVALID)
223 return true; // Can't handle indirect branch.
225 // Conditional branch
226 // Block ends with fall-through condbranch.
228 TBB = LastInst->getOperand(1).getMBB();
229 Cond.push_back(MachineOperand::CreateImm(BranchCode));
230 Cond.push_back(LastInst->getOperand(0));
234 // Get the instruction before it if it's a terminator.
235 MachineInstr *SecondLastInst = I;
237 // If there are three terminators, we don't know what sort of block this is.
238 if (SecondLastInst && I != MBB.begin() &&
239 isUnpredicatedTerminator(--I))
242 unsigned SecondLastOpc = SecondLastInst->getOpcode();
243 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
245 // If the block ends with conditional branch followed by unconditional,
247 if (BranchCode != XCore::COND_INVALID
248 && IsBRU(LastInst->getOpcode())) {
250 TBB = SecondLastInst->getOperand(1).getMBB();
251 Cond.push_back(MachineOperand::CreateImm(BranchCode));
252 Cond.push_back(SecondLastInst->getOperand(0));
254 FBB = LastInst->getOperand(0).getMBB();
258 // If the block ends with two unconditional branches, handle it. The second
259 // one is not executed, so remove it.
260 if (IsBRU(SecondLastInst->getOpcode()) &&
261 IsBRU(LastInst->getOpcode())) {
262 TBB = SecondLastInst->getOperand(0).getMBB();
265 I->eraseFromParent();
269 // Likewise if it ends with a branch table followed by an unconditional branch.
270 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
273 I->eraseFromParent();
277 // Otherwise, can't handle this.
282 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
283 MachineBasicBlock *FBB,
284 const SmallVectorImpl<MachineOperand> &Cond,
286 // Shouldn't be a fall through.
287 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
288 assert((Cond.size() == 2 || Cond.size() == 0) &&
289 "Unexpected number of components!");
291 if (FBB == 0) { // One way branch.
293 // Unconditional branch
294 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
296 // Conditional branch.
297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
298 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
304 // Two-way Conditional branch.
305 assert(Cond.size() == 2 && "Unexpected number of components!");
306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
307 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
309 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
314 XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
315 MachineBasicBlock::iterator I = MBB.end();
316 if (I == MBB.begin()) return 0;
318 while (I->isDebugValue()) {
319 if (I == MBB.begin())
323 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
326 // Remove the branch.
327 I->eraseFromParent();
331 if (I == MBB.begin()) return 1;
333 if (!IsCondBranch(I->getOpcode()))
336 // Remove the branch.
337 I->eraseFromParent();
341 void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
342 MachineBasicBlock::iterator I, DebugLoc DL,
343 unsigned DestReg, unsigned SrcReg,
344 bool KillSrc) const {
345 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
346 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
348 if (GRDest && GRSrc) {
349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
350 .addReg(SrcReg, getKillRegState(KillSrc))
355 if (GRDest && SrcReg == XCore::SP) {
356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
360 if (DestReg == XCore::SP && GRSrc) {
361 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
362 .addReg(SrcReg, getKillRegState(KillSrc));
365 llvm_unreachable("Impossible reg-to-reg copy");
368 void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
369 MachineBasicBlock::iterator I,
370 unsigned SrcReg, bool isKill,
372 const TargetRegisterClass *RC,
373 const TargetRegisterInfo *TRI) const
376 if (I != MBB.end()) DL = I->getDebugLoc();
377 BuildMI(MBB, I, DL, get(XCore::STWFI))
378 .addReg(SrcReg, getKillRegState(isKill))
379 .addFrameIndex(FrameIndex)
383 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
384 MachineBasicBlock::iterator I,
385 unsigned DestReg, int FrameIndex,
386 const TargetRegisterClass *RC,
387 const TargetRegisterInfo *TRI) const
390 if (I != MBB.end()) DL = I->getDebugLoc();
391 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
392 .addFrameIndex(FrameIndex)
396 /// ReverseBranchCondition - Return the inverse opcode of the
397 /// specified Branch instruction.
398 bool XCoreInstrInfo::
399 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
400 assert((Cond.size() == 2) &&
401 "Invalid XCore branch condition!");
402 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
406 static inline bool isImmU6(unsigned val) {
407 return val < (1 << 6);
410 static inline bool isImmU16(unsigned val) {
411 return val < (1 << 16);
414 MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
415 MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator MI,
417 unsigned Reg, uint64_t Value) const {
419 if (MI != MBB.end()) dl = MI->getDebugLoc();
420 if (isMask_32(Value)) {
421 int N = Log2_32(Value) + 1;
422 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N);
424 if (isImmU16(Value)) {
425 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
426 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value);
428 MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
429 const Constant *C = ConstantInt::get(
430 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
431 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
432 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
433 .addConstantPoolIndex(Idx);