1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreInstrInfo.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "XCoreGenInstrInfo.inc"
35 // XCore Condition Codes
47 // Pin the vtable to this file.
48 void XCoreInstrInfo::anchor() {}
50 XCoreInstrInfo::XCoreInstrInfo()
51 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
55 static bool isZeroImm(const MachineOperand &op) {
56 return op.isImm() && op.getImm() == 0;
59 /// isLoadFromStackSlot - If the specified machine instruction is a direct
60 /// load from a stack slot, return the virtual or physical register number of
61 /// the destination along with the FrameIndex of the loaded stack slot. If
62 /// not, return 0. This predicate must return 0 if the instruction has
63 /// any side effects other than loading from the stack slot.
65 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
66 int Opcode = MI->getOpcode();
67 if (Opcode == XCore::LDWFI)
69 if ((MI->getOperand(1).isFI()) && // is a stack slot
70 (MI->getOperand(2).isImm()) && // the imm is zero
71 (isZeroImm(MI->getOperand(2))))
73 FrameIndex = MI->getOperand(1).getIndex();
74 return MI->getOperand(0).getReg();
80 /// isStoreToStackSlot - If the specified machine instruction is a direct
81 /// store to a stack slot, return the virtual or physical register number of
82 /// the source reg along with the FrameIndex of the loaded stack slot. If
83 /// not, return 0. This predicate must return 0 if the instruction has
84 /// any side effects other than storing to the stack slot.
86 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
87 int &FrameIndex) const {
88 int Opcode = MI->getOpcode();
89 if (Opcode == XCore::STWFI)
91 if ((MI->getOperand(1).isFI()) && // is a stack slot
92 (MI->getOperand(2).isImm()) && // the imm is zero
93 (isZeroImm(MI->getOperand(2))))
95 FrameIndex = MI->getOperand(1).getIndex();
96 return MI->getOperand(0).getReg();
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
106 static inline bool IsBRU(unsigned BrOpc) {
107 return BrOpc == XCore::BRFU_u6
108 || BrOpc == XCore::BRFU_lu6
109 || BrOpc == XCore::BRBU_u6
110 || BrOpc == XCore::BRBU_lu6;
113 static inline bool IsBRT(unsigned BrOpc) {
114 return BrOpc == XCore::BRFT_ru6
115 || BrOpc == XCore::BRFT_lru6
116 || BrOpc == XCore::BRBT_ru6
117 || BrOpc == XCore::BRBT_lru6;
120 static inline bool IsBRF(unsigned BrOpc) {
121 return BrOpc == XCore::BRFF_ru6
122 || BrOpc == XCore::BRFF_lru6
123 || BrOpc == XCore::BRBF_ru6
124 || BrOpc == XCore::BRBF_lru6;
127 static inline bool IsCondBranch(unsigned BrOpc) {
128 return IsBRF(BrOpc) || IsBRT(BrOpc);
131 static inline bool IsBR_JT(unsigned BrOpc) {
132 return BrOpc == XCore::BR_JT
133 || BrOpc == XCore::BR_JT32;
136 /// GetCondFromBranchOpc - Return the XCore CC that matches
137 /// the correspondent Branch instruction opcode.
138 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
141 return XCore::COND_TRUE;
142 } else if (IsBRF(BrOpc)) {
143 return XCore::COND_FALSE;
145 return XCore::COND_INVALID;
149 /// GetCondBranchFromCond - Return the Branch instruction
150 /// opcode that matches the cc.
151 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
154 default: llvm_unreachable("Illegal condition code!");
155 case XCore::COND_TRUE : return XCore::BRFT_lru6;
156 case XCore::COND_FALSE : return XCore::BRFF_lru6;
160 /// GetOppositeBranchCondition - Return the inverse of the specified
161 /// condition, e.g. turning COND_E to COND_NE.
162 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
165 default: llvm_unreachable("Illegal condition code!");
166 case XCore::COND_TRUE : return XCore::COND_FALSE;
167 case XCore::COND_FALSE : return XCore::COND_TRUE;
171 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
172 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
173 /// implemented for a target). Upon success, this returns false and returns
174 /// with the following information in various cases:
176 /// 1. If this block ends with no branches (it just falls through to its succ)
177 /// just return false, leaving TBB/FBB null.
178 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
179 /// the destination block.
180 /// 3. If this block ends with an conditional branch and it falls through to
181 /// an successor block, it sets TBB to be the branch destination block and a
182 /// list of operands that evaluate the condition. These
183 /// operands can be passed to other TargetInstrInfo methods to create new
185 /// 4. If this block ends with an conditional branch and an unconditional
186 /// block, it returns the 'true' destination in TBB, the 'false' destination
187 /// in FBB, and a list of operands that evaluate the condition. These
188 /// operands can be passed to other TargetInstrInfo methods to create new
191 /// Note that RemoveBranch and InsertBranch must be implemented to support
192 /// cases where this method returns success.
195 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
196 MachineBasicBlock *&FBB,
197 SmallVectorImpl<MachineOperand> &Cond,
198 bool AllowModify) const {
199 // If the block has no terminators, it just falls into the block after it.
200 MachineBasicBlock::iterator I = MBB.end();
201 if (I == MBB.begin())
204 while (I->isDebugValue()) {
205 if (I == MBB.begin())
209 if (!isUnpredicatedTerminator(I))
212 // Get the last instruction in the block.
213 MachineInstr *LastInst = I;
215 // If there is only one terminator instruction, process it.
216 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
217 if (IsBRU(LastInst->getOpcode())) {
218 TBB = LastInst->getOperand(0).getMBB();
222 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
223 if (BranchCode == XCore::COND_INVALID)
224 return true; // Can't handle indirect branch.
226 // Conditional branch
227 // Block ends with fall-through condbranch.
229 TBB = LastInst->getOperand(1).getMBB();
230 Cond.push_back(MachineOperand::CreateImm(BranchCode));
231 Cond.push_back(LastInst->getOperand(0));
235 // Get the instruction before it if it's a terminator.
236 MachineInstr *SecondLastInst = I;
238 // If there are three terminators, we don't know what sort of block this is.
239 if (SecondLastInst && I != MBB.begin() &&
240 isUnpredicatedTerminator(--I))
243 unsigned SecondLastOpc = SecondLastInst->getOpcode();
244 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
246 // If the block ends with conditional branch followed by unconditional,
248 if (BranchCode != XCore::COND_INVALID
249 && IsBRU(LastInst->getOpcode())) {
251 TBB = SecondLastInst->getOperand(1).getMBB();
252 Cond.push_back(MachineOperand::CreateImm(BranchCode));
253 Cond.push_back(SecondLastInst->getOperand(0));
255 FBB = LastInst->getOperand(0).getMBB();
259 // If the block ends with two unconditional branches, handle it. The second
260 // one is not executed, so remove it.
261 if (IsBRU(SecondLastInst->getOpcode()) &&
262 IsBRU(LastInst->getOpcode())) {
263 TBB = SecondLastInst->getOperand(0).getMBB();
266 I->eraseFromParent();
270 // Likewise if it ends with a branch table followed by an unconditional branch.
271 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
274 I->eraseFromParent();
278 // Otherwise, can't handle this.
283 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
284 MachineBasicBlock *FBB,
285 const SmallVectorImpl<MachineOperand> &Cond,
287 // Shouldn't be a fall through.
288 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
289 assert((Cond.size() == 2 || Cond.size() == 0) &&
290 "Unexpected number of components!");
292 if (FBB == 0) { // One way branch.
294 // Unconditional branch
295 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
297 // Conditional branch.
298 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
305 // Two-way Conditional branch.
306 assert(Cond.size() == 2 && "Unexpected number of components!");
307 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
308 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
310 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
315 XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
316 MachineBasicBlock::iterator I = MBB.end();
317 if (I == MBB.begin()) return 0;
319 while (I->isDebugValue()) {
320 if (I == MBB.begin())
324 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
327 // Remove the branch.
328 I->eraseFromParent();
332 if (I == MBB.begin()) return 1;
334 if (!IsCondBranch(I->getOpcode()))
337 // Remove the branch.
338 I->eraseFromParent();
342 void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
343 MachineBasicBlock::iterator I, DebugLoc DL,
344 unsigned DestReg, unsigned SrcReg,
345 bool KillSrc) const {
346 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
347 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
349 if (GRDest && GRSrc) {
350 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
351 .addReg(SrcReg, getKillRegState(KillSrc))
356 if (GRDest && SrcReg == XCore::SP) {
357 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
361 if (DestReg == XCore::SP && GRSrc) {
362 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
363 .addReg(SrcReg, getKillRegState(KillSrc));
366 llvm_unreachable("Impossible reg-to-reg copy");
369 void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
370 MachineBasicBlock::iterator I,
371 unsigned SrcReg, bool isKill,
373 const TargetRegisterClass *RC,
374 const TargetRegisterInfo *TRI) const
377 if (I != MBB.end()) DL = I->getDebugLoc();
378 MachineFunction *MF = MBB.getParent();
379 const MachineFrameInfo &MFI = *MF->getFrameInfo();
380 MachineMemOperand *MMO =
381 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
382 MachineMemOperand::MOStore,
383 MFI.getObjectSize(FrameIndex),
384 MFI.getObjectAlignment(FrameIndex));
385 BuildMI(MBB, I, DL, get(XCore::STWFI))
386 .addReg(SrcReg, getKillRegState(isKill))
387 .addFrameIndex(FrameIndex)
392 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator I,
394 unsigned DestReg, int FrameIndex,
395 const TargetRegisterClass *RC,
396 const TargetRegisterInfo *TRI) const
399 if (I != MBB.end()) DL = I->getDebugLoc();
400 MachineFunction *MF = MBB.getParent();
401 const MachineFrameInfo &MFI = *MF->getFrameInfo();
402 MachineMemOperand *MMO =
403 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIndex),
404 MachineMemOperand::MOLoad,
405 MFI.getObjectSize(FrameIndex),
406 MFI.getObjectAlignment(FrameIndex));
407 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
408 .addFrameIndex(FrameIndex)
413 /// ReverseBranchCondition - Return the inverse opcode of the
414 /// specified Branch instruction.
415 bool XCoreInstrInfo::
416 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
417 assert((Cond.size() == 2) &&
418 "Invalid XCore branch condition!");
419 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
423 static inline bool isImmU6(unsigned val) {
424 return val < (1 << 6);
427 static inline bool isImmU16(unsigned val) {
428 return val < (1 << 16);
431 MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
432 MachineBasicBlock &MBB,
433 MachineBasicBlock::iterator MI,
434 unsigned Reg, uint64_t Value) const {
436 if (MI != MBB.end()) dl = MI->getDebugLoc();
437 if (isMask_32(Value)) {
438 int N = Log2_32(Value) + 1;
439 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N);
441 if (isImmU16(Value)) {
442 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
443 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value);
445 MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
446 const Constant *C = ConstantInt::get(
447 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
448 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
449 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
450 .addConstantPoolIndex(Idx);