1 //===- XCoreInstrInfo.cpp - XCore Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreMachineFunctionInfo.h"
15 #include "XCoreInstrInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
25 #define GET_INSTRINFO_CTOR
26 #define GET_INSTRINFO_MC_DESC
27 #include "XCoreGenInstrInfo.inc"
32 // XCore Condition Codes
43 XCoreInstrInfo::XCoreInstrInfo()
44 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
48 static bool isZeroImm(const MachineOperand &op) {
49 return op.isImm() && op.getImm() == 0;
52 /// isLoadFromStackSlot - If the specified machine instruction is a direct
53 /// load from a stack slot, return the virtual or physical register number of
54 /// the destination along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than loading from the stack slot.
58 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
59 int Opcode = MI->getOpcode();
60 if (Opcode == XCore::LDWFI)
62 if ((MI->getOperand(1).isFI()) && // is a stack slot
63 (MI->getOperand(2).isImm()) && // the imm is zero
64 (isZeroImm(MI->getOperand(2))))
66 FrameIndex = MI->getOperand(1).getIndex();
67 return MI->getOperand(0).getReg();
73 /// isStoreToStackSlot - If the specified machine instruction is a direct
74 /// store to a stack slot, return the virtual or physical register number of
75 /// the source reg along with the FrameIndex of the loaded stack slot. If
76 /// not, return 0. This predicate must return 0 if the instruction has
77 /// any side effects other than storing to the stack slot.
79 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
80 int &FrameIndex) const {
81 int Opcode = MI->getOpcode();
82 if (Opcode == XCore::STWFI)
84 if ((MI->getOperand(1).isFI()) && // is a stack slot
85 (MI->getOperand(2).isImm()) && // the imm is zero
86 (isZeroImm(MI->getOperand(2))))
88 FrameIndex = MI->getOperand(1).getIndex();
89 return MI->getOperand(0).getReg();
95 //===----------------------------------------------------------------------===//
97 //===----------------------------------------------------------------------===//
99 static inline bool IsBRU(unsigned BrOpc) {
100 return BrOpc == XCore::BRFU_u6
101 || BrOpc == XCore::BRFU_lu6
102 || BrOpc == XCore::BRBU_u6
103 || BrOpc == XCore::BRBU_lu6;
106 static inline bool IsBRT(unsigned BrOpc) {
107 return BrOpc == XCore::BRFT_ru6
108 || BrOpc == XCore::BRFT_lru6
109 || BrOpc == XCore::BRBT_ru6
110 || BrOpc == XCore::BRBT_lru6;
113 static inline bool IsBRF(unsigned BrOpc) {
114 return BrOpc == XCore::BRFF_ru6
115 || BrOpc == XCore::BRFF_lru6
116 || BrOpc == XCore::BRBF_ru6
117 || BrOpc == XCore::BRBF_lru6;
120 static inline bool IsCondBranch(unsigned BrOpc) {
121 return IsBRF(BrOpc) || IsBRT(BrOpc);
124 static inline bool IsBR_JT(unsigned BrOpc) {
125 return BrOpc == XCore::BR_JT
126 || BrOpc == XCore::BR_JT32;
129 /// GetCondFromBranchOpc - Return the XCore CC that matches
130 /// the correspondent Branch instruction opcode.
131 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
134 return XCore::COND_TRUE;
135 } else if (IsBRF(BrOpc)) {
136 return XCore::COND_FALSE;
138 return XCore::COND_INVALID;
142 /// GetCondBranchFromCond - Return the Branch instruction
143 /// opcode that matches the cc.
144 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
147 default: llvm_unreachable("Illegal condition code!");
148 case XCore::COND_TRUE : return XCore::BRFT_lru6;
149 case XCore::COND_FALSE : return XCore::BRFF_lru6;
153 /// GetOppositeBranchCondition - Return the inverse of the specified
154 /// condition, e.g. turning COND_E to COND_NE.
155 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
158 default: llvm_unreachable("Illegal condition code!");
159 case XCore::COND_TRUE : return XCore::COND_FALSE;
160 case XCore::COND_FALSE : return XCore::COND_TRUE;
164 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
165 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
166 /// implemented for a target). Upon success, this returns false and returns
167 /// with the following information in various cases:
169 /// 1. If this block ends with no branches (it just falls through to its succ)
170 /// just return false, leaving TBB/FBB null.
171 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
172 /// the destination block.
173 /// 3. If this block ends with an conditional branch and it falls through to
174 /// an successor block, it sets TBB to be the branch destination block and a
175 /// list of operands that evaluate the condition. These
176 /// operands can be passed to other TargetInstrInfo methods to create new
178 /// 4. If this block ends with an conditional branch and an unconditional
179 /// block, it returns the 'true' destination in TBB, the 'false' destination
180 /// in FBB, and a list of operands that evaluate the condition. These
181 /// operands can be passed to other TargetInstrInfo methods to create new
184 /// Note that RemoveBranch and InsertBranch must be implemented to support
185 /// cases where this method returns success.
188 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
189 MachineBasicBlock *&FBB,
190 SmallVectorImpl<MachineOperand> &Cond,
191 bool AllowModify) const {
192 // If the block has no terminators, it just falls into the block after it.
193 MachineBasicBlock::iterator I = MBB.end();
194 if (I == MBB.begin())
197 while (I->isDebugValue()) {
198 if (I == MBB.begin())
202 if (!isUnpredicatedTerminator(I))
205 // Get the last instruction in the block.
206 MachineInstr *LastInst = I;
208 // If there is only one terminator instruction, process it.
209 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
210 if (IsBRU(LastInst->getOpcode())) {
211 TBB = LastInst->getOperand(0).getMBB();
215 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
216 if (BranchCode == XCore::COND_INVALID)
217 return true; // Can't handle indirect branch.
219 // Conditional branch
220 // Block ends with fall-through condbranch.
222 TBB = LastInst->getOperand(1).getMBB();
223 Cond.push_back(MachineOperand::CreateImm(BranchCode));
224 Cond.push_back(LastInst->getOperand(0));
228 // Get the instruction before it if it's a terminator.
229 MachineInstr *SecondLastInst = I;
231 // If there are three terminators, we don't know what sort of block this is.
232 if (SecondLastInst && I != MBB.begin() &&
233 isUnpredicatedTerminator(--I))
236 unsigned SecondLastOpc = SecondLastInst->getOpcode();
237 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
239 // If the block ends with conditional branch followed by unconditional,
241 if (BranchCode != XCore::COND_INVALID
242 && IsBRU(LastInst->getOpcode())) {
244 TBB = SecondLastInst->getOperand(1).getMBB();
245 Cond.push_back(MachineOperand::CreateImm(BranchCode));
246 Cond.push_back(SecondLastInst->getOperand(0));
248 FBB = LastInst->getOperand(0).getMBB();
252 // If the block ends with two unconditional branches, handle it. The second
253 // one is not executed, so remove it.
254 if (IsBRU(SecondLastInst->getOpcode()) &&
255 IsBRU(LastInst->getOpcode())) {
256 TBB = SecondLastInst->getOperand(0).getMBB();
259 I->eraseFromParent();
263 // Likewise if it ends with a branch table followed by an unconditional branch.
264 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
267 I->eraseFromParent();
271 // Otherwise, can't handle this.
276 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
277 MachineBasicBlock *FBB,
278 const SmallVectorImpl<MachineOperand> &Cond,
280 // Shouldn't be a fall through.
281 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
282 assert((Cond.size() == 2 || Cond.size() == 0) &&
283 "Unexpected number of components!");
285 if (FBB == 0) { // One way branch.
287 // Unconditional branch
288 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
290 // Conditional branch.
291 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
292 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
298 // Two-way Conditional branch.
299 assert(Cond.size() == 2 && "Unexpected number of components!");
300 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
301 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
303 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
308 XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
309 MachineBasicBlock::iterator I = MBB.end();
310 if (I == MBB.begin()) return 0;
312 while (I->isDebugValue()) {
313 if (I == MBB.begin())
317 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
320 // Remove the branch.
321 I->eraseFromParent();
325 if (I == MBB.begin()) return 1;
327 if (!IsCondBranch(I->getOpcode()))
330 // Remove the branch.
331 I->eraseFromParent();
335 void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
336 MachineBasicBlock::iterator I, DebugLoc DL,
337 unsigned DestReg, unsigned SrcReg,
338 bool KillSrc) const {
339 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
340 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
342 if (GRDest && GRSrc) {
343 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
344 .addReg(SrcReg, getKillRegState(KillSrc))
349 if (GRDest && SrcReg == XCore::SP) {
350 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
354 if (DestReg == XCore::SP && GRSrc) {
355 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
356 .addReg(SrcReg, getKillRegState(KillSrc));
359 llvm_unreachable("Impossible reg-to-reg copy");
362 void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
363 MachineBasicBlock::iterator I,
364 unsigned SrcReg, bool isKill,
366 const TargetRegisterClass *RC,
367 const TargetRegisterInfo *TRI) const
370 if (I != MBB.end()) DL = I->getDebugLoc();
371 BuildMI(MBB, I, DL, get(XCore::STWFI))
372 .addReg(SrcReg, getKillRegState(isKill))
373 .addFrameIndex(FrameIndex)
377 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
378 MachineBasicBlock::iterator I,
379 unsigned DestReg, int FrameIndex,
380 const TargetRegisterClass *RC,
381 const TargetRegisterInfo *TRI) const
384 if (I != MBB.end()) DL = I->getDebugLoc();
385 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
386 .addFrameIndex(FrameIndex)
390 /// ReverseBranchCondition - Return the inverse opcode of the
391 /// specified Branch instruction.
392 bool XCoreInstrInfo::
393 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
394 assert((Cond.size() == 2) &&
395 "Invalid XCore branch condition!");
396 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));