1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreInstrInfo.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/TargetRegistry.h"
31 #define GET_INSTRINFO_CTOR_DTOR
32 #include "XCoreGenInstrInfo.inc"
37 // XCore Condition Codes
46 // Pin the vtable to this file.
47 void XCoreInstrInfo::anchor() {}
49 XCoreInstrInfo::XCoreInstrInfo()
50 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
54 static bool isZeroImm(const MachineOperand &op) {
55 return op.isImm() && op.getImm() == 0;
58 /// isLoadFromStackSlot - If the specified machine instruction is a direct
59 /// load from a stack slot, return the virtual or physical register number of
60 /// the destination along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than loading from the stack slot.
64 XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{
65 int Opcode = MI->getOpcode();
66 if (Opcode == XCore::LDWFI)
68 if ((MI->getOperand(1).isFI()) && // is a stack slot
69 (MI->getOperand(2).isImm()) && // the imm is zero
70 (isZeroImm(MI->getOperand(2))))
72 FrameIndex = MI->getOperand(1).getIndex();
73 return MI->getOperand(0).getReg();
79 /// isStoreToStackSlot - If the specified machine instruction is a direct
80 /// store to a stack slot, return the virtual or physical register number of
81 /// the source reg along with the FrameIndex of the loaded stack slot. If
82 /// not, return 0. This predicate must return 0 if the instruction has
83 /// any side effects other than storing to the stack slot.
85 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
86 int &FrameIndex) const {
87 int Opcode = MI->getOpcode();
88 if (Opcode == XCore::STWFI)
90 if ((MI->getOperand(1).isFI()) && // is a stack slot
91 (MI->getOperand(2).isImm()) && // the imm is zero
92 (isZeroImm(MI->getOperand(2))))
94 FrameIndex = MI->getOperand(1).getIndex();
95 return MI->getOperand(0).getReg();
101 //===----------------------------------------------------------------------===//
103 //===----------------------------------------------------------------------===//
105 static inline bool IsBRU(unsigned BrOpc) {
106 return BrOpc == XCore::BRFU_u6
107 || BrOpc == XCore::BRFU_lu6
108 || BrOpc == XCore::BRBU_u6
109 || BrOpc == XCore::BRBU_lu6;
112 static inline bool IsBRT(unsigned BrOpc) {
113 return BrOpc == XCore::BRFT_ru6
114 || BrOpc == XCore::BRFT_lru6
115 || BrOpc == XCore::BRBT_ru6
116 || BrOpc == XCore::BRBT_lru6;
119 static inline bool IsBRF(unsigned BrOpc) {
120 return BrOpc == XCore::BRFF_ru6
121 || BrOpc == XCore::BRFF_lru6
122 || BrOpc == XCore::BRBF_ru6
123 || BrOpc == XCore::BRBF_lru6;
126 static inline bool IsCondBranch(unsigned BrOpc) {
127 return IsBRF(BrOpc) || IsBRT(BrOpc);
130 static inline bool IsBR_JT(unsigned BrOpc) {
131 return BrOpc == XCore::BR_JT
132 || BrOpc == XCore::BR_JT32;
135 /// GetCondFromBranchOpc - Return the XCore CC that matches
136 /// the correspondent Branch instruction opcode.
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
140 return XCore::COND_TRUE;
141 } else if (IsBRF(BrOpc)) {
142 return XCore::COND_FALSE;
144 return XCore::COND_INVALID;
148 /// GetCondBranchFromCond - Return the Branch instruction
149 /// opcode that matches the cc.
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
153 default: llvm_unreachable("Illegal condition code!");
154 case XCore::COND_TRUE : return XCore::BRFT_lru6;
155 case XCore::COND_FALSE : return XCore::BRFF_lru6;
159 /// GetOppositeBranchCondition - Return the inverse of the specified
160 /// condition, e.g. turning COND_E to COND_NE.
161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
164 default: llvm_unreachable("Illegal condition code!");
165 case XCore::COND_TRUE : return XCore::COND_FALSE;
166 case XCore::COND_FALSE : return XCore::COND_TRUE;
170 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
171 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
172 /// implemented for a target). Upon success, this returns false and returns
173 /// with the following information in various cases:
175 /// 1. If this block ends with no branches (it just falls through to its succ)
176 /// just return false, leaving TBB/FBB null.
177 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
178 /// the destination block.
179 /// 3. If this block ends with an conditional branch and it falls through to
180 /// an successor block, it sets TBB to be the branch destination block and a
181 /// list of operands that evaluate the condition. These
182 /// operands can be passed to other TargetInstrInfo methods to create new
184 /// 4. If this block ends with an conditional branch and an unconditional
185 /// block, it returns the 'true' destination in TBB, the 'false' destination
186 /// in FBB, and a list of operands that evaluate the condition. These
187 /// operands can be passed to other TargetInstrInfo methods to create new
190 /// Note that RemoveBranch and InsertBranch must be implemented to support
191 /// cases where this method returns success.
194 XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
195 MachineBasicBlock *&FBB,
196 SmallVectorImpl<MachineOperand> &Cond,
197 bool AllowModify) const {
198 // If the block has no terminators, it just falls into the block after it.
199 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
203 if (!isUnpredicatedTerminator(I))
206 // Get the last instruction in the block.
207 MachineInstr *LastInst = I;
209 // If there is only one terminator instruction, process it.
210 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
211 if (IsBRU(LastInst->getOpcode())) {
212 TBB = LastInst->getOperand(0).getMBB();
216 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
217 if (BranchCode == XCore::COND_INVALID)
218 return true; // Can't handle indirect branch.
220 // Conditional branch
221 // Block ends with fall-through condbranch.
223 TBB = LastInst->getOperand(1).getMBB();
224 Cond.push_back(MachineOperand::CreateImm(BranchCode));
225 Cond.push_back(LastInst->getOperand(0));
229 // Get the instruction before it if it's a terminator.
230 MachineInstr *SecondLastInst = I;
232 // If there are three terminators, we don't know what sort of block this is.
233 if (SecondLastInst && I != MBB.begin() &&
234 isUnpredicatedTerminator(--I))
237 unsigned SecondLastOpc = SecondLastInst->getOpcode();
238 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
240 // If the block ends with conditional branch followed by unconditional,
242 if (BranchCode != XCore::COND_INVALID
243 && IsBRU(LastInst->getOpcode())) {
245 TBB = SecondLastInst->getOperand(1).getMBB();
246 Cond.push_back(MachineOperand::CreateImm(BranchCode));
247 Cond.push_back(SecondLastInst->getOperand(0));
249 FBB = LastInst->getOperand(0).getMBB();
253 // If the block ends with two unconditional branches, handle it. The second
254 // one is not executed, so remove it.
255 if (IsBRU(SecondLastInst->getOpcode()) &&
256 IsBRU(LastInst->getOpcode())) {
257 TBB = SecondLastInst->getOperand(0).getMBB();
260 I->eraseFromParent();
264 // Likewise if it ends with a branch table followed by an unconditional branch.
265 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
268 I->eraseFromParent();
272 // Otherwise, can't handle this.
277 XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
278 MachineBasicBlock *FBB,
279 ArrayRef<MachineOperand> Cond,
281 // Shouldn't be a fall through.
282 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
283 assert((Cond.size() == 2 || Cond.size() == 0) &&
284 "Unexpected number of components!");
286 if (!FBB) { // One way branch.
288 // Unconditional branch
289 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
291 // Conditional branch.
292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
293 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 // Two-way Conditional branch.
300 assert(Cond.size() == 2 && "Unexpected number of components!");
301 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
302 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
304 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
309 XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
310 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
314 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
317 // Remove the branch.
318 I->eraseFromParent();
322 if (I == MBB.begin()) return 1;
324 if (!IsCondBranch(I->getOpcode()))
327 // Remove the branch.
328 I->eraseFromParent();
332 void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
333 MachineBasicBlock::iterator I, DebugLoc DL,
334 unsigned DestReg, unsigned SrcReg,
335 bool KillSrc) const {
336 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
337 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
339 if (GRDest && GRSrc) {
340 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
341 .addReg(SrcReg, getKillRegState(KillSrc))
346 if (GRDest && SrcReg == XCore::SP) {
347 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
351 if (DestReg == XCore::SP && GRSrc) {
352 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
353 .addReg(SrcReg, getKillRegState(KillSrc));
356 llvm_unreachable("Impossible reg-to-reg copy");
359 void XCoreInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
360 MachineBasicBlock::iterator I,
361 unsigned SrcReg, bool isKill,
363 const TargetRegisterClass *RC,
364 const TargetRegisterInfo *TRI) const
367 if (I != MBB.end() && !I->isDebugValue())
368 DL = I->getDebugLoc();
369 MachineFunction *MF = MBB.getParent();
370 const MachineFrameInfo &MFI = *MF->getFrameInfo();
371 MachineMemOperand *MMO = MF->getMachineMemOperand(
372 MachinePointerInfo::getFixedStack(*MF, FrameIndex),
373 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
374 MFI.getObjectAlignment(FrameIndex));
375 BuildMI(MBB, I, DL, get(XCore::STWFI))
376 .addReg(SrcReg, getKillRegState(isKill))
377 .addFrameIndex(FrameIndex)
382 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator I,
384 unsigned DestReg, int FrameIndex,
385 const TargetRegisterClass *RC,
386 const TargetRegisterInfo *TRI) const
389 if (I != MBB.end() && !I->isDebugValue())
390 DL = I->getDebugLoc();
391 MachineFunction *MF = MBB.getParent();
392 const MachineFrameInfo &MFI = *MF->getFrameInfo();
393 MachineMemOperand *MMO = MF->getMachineMemOperand(
394 MachinePointerInfo::getFixedStack(*MF, FrameIndex),
395 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
396 MFI.getObjectAlignment(FrameIndex));
397 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
398 .addFrameIndex(FrameIndex)
403 /// ReverseBranchCondition - Return the inverse opcode of the
404 /// specified Branch instruction.
405 bool XCoreInstrInfo::
406 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
407 assert((Cond.size() == 2) &&
408 "Invalid XCore branch condition!");
409 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
413 static inline bool isImmU6(unsigned val) {
414 return val < (1 << 6);
417 static inline bool isImmU16(unsigned val) {
418 return val < (1 << 16);
421 static bool isImmMskBitp(unsigned val) {
422 if (!isMask_32(val)) {
425 int N = Log2_32(val) + 1;
426 return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
429 MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
430 MachineBasicBlock &MBB,
431 MachineBasicBlock::iterator MI,
432 unsigned Reg, uint64_t Value) const {
434 if (MI != MBB.end() && !MI->isDebugValue())
435 dl = MI->getDebugLoc();
436 if (isImmMskBitp(Value)) {
437 int N = Log2_32(Value) + 1;
438 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
442 if (isImmU16(Value)) {
443 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
444 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
446 MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
447 const Constant *C = ConstantInt::get(
448 Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
449 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
450 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
451 .addConstantPoolIndex(Idx)