1 //===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef XCOREINSTRUCTIONINFO_H
15 #define XCOREINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "XCoreRegisterInfo.h"
22 class XCoreInstrInfo : public TargetInstrInfoImpl {
23 const XCoreRegisterInfo RI;
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
31 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
46 /// isStoreToStackSlot - If the specified machine instruction is a direct
47 /// store to a stack slot, return the virtual or physical register number of
48 /// the source reg along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than storing to the stack slot.
51 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
53 virtual bool isInvariantLoad(MachineInstr *MI) const;
55 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
56 MachineBasicBlock *&FBB,
57 SmallVectorImpl<MachineOperand> &Cond) const;
59 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
60 MachineBasicBlock *FBB,
61 const SmallVectorImpl<MachineOperand> &Cond) const;
63 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
65 virtual bool copyRegToReg(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator I,
67 unsigned DestReg, unsigned SrcReg,
68 const TargetRegisterClass *DestRC,
69 const TargetRegisterClass *SrcRC) const;
71 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MI,
73 unsigned SrcReg, bool isKill, int FrameIndex,
74 const TargetRegisterClass *RC) const;
76 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
77 SmallVectorImpl<MachineOperand> &Addr,
78 const TargetRegisterClass *RC,
79 SmallVectorImpl<MachineInstr*> &NewMIs) const;
81 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MI,
83 unsigned DestReg, int FrameIndex,
84 const TargetRegisterClass *RC) const;
86 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
87 SmallVectorImpl<MachineOperand> &Addr,
88 const TargetRegisterClass *RC,
89 SmallVectorImpl<MachineInstr*> &NewMIs) const;
91 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator MI,
93 const std::vector<CalleeSavedInfo> &CSI) const;
95 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MI,
97 const std::vector<CalleeSavedInfo> &CSI) const;
99 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
101 virtual bool ReverseBranchCondition(
102 SmallVectorImpl<MachineOperand> &Cond) const;