1 //===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef XCOREINSTRUCTIONINFO_H
15 #define XCOREINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "XCoreRegisterInfo.h"
22 class XCoreInstrInfo : public TargetInstrInfoImpl {
23 const XCoreRegisterInfo RI;
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
31 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
45 int &FrameIndex) const;
47 /// isStoreToStackSlot - If the specified machine instruction is a direct
48 /// store to a stack slot, return the virtual or physical register number of
49 /// the source reg along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than storing to the stack slot.
52 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const;
55 virtual bool isInvariantLoad(const MachineInstr *MI) const;
57 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
58 MachineBasicBlock *&FBB,
59 SmallVectorImpl<MachineOperand> &Cond) const;
61 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
62 MachineBasicBlock *FBB,
63 const SmallVectorImpl<MachineOperand> &Cond) const;
65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
67 virtual bool copyRegToReg(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator I,
69 unsigned DestReg, unsigned SrcReg,
70 const TargetRegisterClass *DestRC,
71 const TargetRegisterClass *SrcRC) const;
73 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MI,
75 unsigned SrcReg, bool isKill, int FrameIndex,
76 const TargetRegisterClass *RC) const;
78 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
79 SmallVectorImpl<MachineOperand> &Addr,
80 const TargetRegisterClass *RC,
81 SmallVectorImpl<MachineInstr*> &NewMIs) const;
83 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
84 MachineBasicBlock::iterator MI,
85 unsigned DestReg, int FrameIndex,
86 const TargetRegisterClass *RC) const;
88 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
89 SmallVectorImpl<MachineOperand> &Addr,
90 const TargetRegisterClass *RC,
91 SmallVectorImpl<MachineInstr*> &NewMIs) const;
93 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator MI,
95 const std::vector<CalleeSavedInfo> &CSI) const;
97 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 const std::vector<CalleeSavedInfo> &CSI) const;
101 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
103 virtual bool ReverseBranchCondition(
104 SmallVectorImpl<MachineOperand> &Cond) const;